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1. 发明授权

US6026505A Method and apparatus for real time two dimensional redundancy allocation 失效
标题翻译：用于实时二维冗余分配的方法和装置
公开(公告)号：US6026505A
公开(公告)日：2000-02-15
申请号：US777877
申请日：1991-10-16
申请人： Erik Leigh Hedberg , Garrett Stephen Koch
发明人： Erik Leigh Hedberg , Garrett Stephen Koch
IPC分类号： G06F12/16 , G11C29/00 , G11C29/04 , G11C29/12 , G11C29/44 , G11C29/56 , G06F11/00
CPC分类号： G11C29/72 , G11C29/44
摘要： A method and apparatus are provided in an array built in self test (ABIST) environment formed on a semiconductor chip having an array of memory cells arranged in columns and rows and column and row redundant lines which includes testing the array along the columns to identify a given number of faulty cells in each of the columns, storing the column addresses having the given number of faulty cells in first registers, further testing the array along the columns or rows to identify any additional faulty cells while masking the cells having the stored column addresses and storing the row addresses having the faulty cell in second registers until all of the second registers store row addresses, and after all of the second registers store row addresses, continue testing the array while masking the cells having the stored column or row addresses and storing the column addresses of any remaining additional faulty cell in any unused register of the first registers.
摘要翻译：一种方法和装置被提供在一个内置在自检（ABIST）环境中的阵列中，该阵列形成在半导体芯片上，该半导体芯片具有排列成列和行的存储单元阵列以及列和行冗余线，其包括沿着列测试阵列以识别给定数量的每个列中的故障单元，将具有给定数量的故障单元的列地址存储在第一寄存器中，进一步沿列或行测试该阵列以识别任何附加的故障单元，同时掩蔽具有存储的列地址的单元并且将具有故障单元的行地址存储在第二寄存器中，直到所有第二寄存器存储行地址，并且在所有第二寄存器存储行地址之后，继续测试阵列，同时屏蔽具有存储的列或行地址的单元并存储第一个寄存器的任何未使用的寄存器中任何剩余的附加故障单元的列地址。

2. 发明授权

US5771242A Memory array built-in self-test circuit having a programmable pattern generator for allowing unique read/write operations to adjacent memory cells, and method therefor 失效
标题翻译：具有可编程模式发生器的内存自检电路的存储器阵列，用于允许对相邻存储单元的唯一的读/写操作及其方法
公开(公告)号：US5771242A
公开(公告)日：1998-06-23
申请号：US721601
申请日：1996-09-25
申请人： Robert Dean Adams , John Connor , Garrett Stephen Koch , Luigi Ternullo, Jr.
发明人： Robert Dean Adams , John Connor , Garrett Stephen Koch , Luigi Ternullo, Jr.
IPC分类号： G11C29/12 , G11C29/10 , G11C29/36 , G01R31/28
CPC分类号： G11C29/36
摘要： An ABIST circuit for testing a memory array has a blanket write subcycle (WC), an RC.sub.3 subcycle, and an RC.sub.4 subcycle. The ABIST circuit includes a programmable pattern generator that provides eight programmable data bits, eight programmable read/write bits, and two programmable address frequency bits to determine the specific test patterns applied to the memory array. The address frequency bits determine how many memory cycles will be performed on each cell of the memory array. In X1 mode, only one memory cycle is performed on each cell during any given subcycle. In X2 mode, two memory cycles are performed on each cell, allowing a cell to be written, then subsequently read in the same subcycle, In X4 mode, four memory cycles are performed on each cell, and in Xg mode, all eight bits of read/write and data are used on each cell, resulting in eight memory cycles for each cell within the memory array.
摘要翻译：用于测试存储器阵列的ABIST电路具有毯子写入子周期（WC），RC3子周期和RC4子周期。 ABIST电路包括一个可编程模式发生器，提供八个可编程数据位，八个可编程读/写位和两个可编程地址频率位，以确定应用于存储器阵列的特定测试模式。地址频率位决定在存储器阵列的每个单元上执行多少个内存周期。在X1模式下，在任何给定的子周期内，每个单元只执行一个存储周期。在X2模式下，对每个单元执行两个存储周期，允许单元被写入，然后在相同的子周期中读取。在X4模式下，对每个单元执行四个存储周期，而在Xg模式下，所有8位在每个单元上使用读/写和数据，从而为存储器阵列内的每个单元产生8个存储周期。

3. 发明授权

US5761213A Method and apparatus to determine erroneous value in memory cells using data compression 失效
标题翻译：使用数据压缩来确定存储器单元中的错误值的方法和装置
公开(公告)号：US5761213A
公开(公告)日：1998-06-02
申请号：US603963
申请日：1996-02-20
申请人： Robert Dean Adams , John Connor , Garrett Stephen Koch , Luigi Ternullo, Jr.
发明人： Robert Dean Adams , John Connor , Garrett Stephen Koch , Luigi Ternullo, Jr.
IPC分类号： G01R31/26 , G01R31/28 , G01R31/3185 , G06F7/02 , G11C29/00 , G11C29/12 , G11C29/26 , G11C29/40 , G11C29/56 , H01L21/66
CPC分类号： G11C29/26 , G01R31/318527 , G06F7/02 , G11C29/40
摘要： A method and circuit are provided to detect if any bit stored in a given location in a memory is different from the data expected. The circuit includes logic to read each of the bits stored in the cells at given locations from memory and to generate a fail signal based on the data expected to be stored if the stored data is different from the expected data. The circuit also preferably includes logic to compare the True data and expect data read from each cell and generating the fail signal if they are the same. Additional logic circuitry is also preferably provided which determines if a node of the circuit remains in a precharged condition.
摘要翻译：提供了一种方法和电路来检测存储在存储器中的给定位置中的任何位是否与预期的数据不同。该电路包括从存储器中的给定位置读取存储在单元中的每个位的逻辑，并且如果存储的数据与预期数据不同，则基于预期存储的数据生成失败信号。该电路还优选地包括用于比较True数据并期望从每个单元读取的数据的逻辑，并且如果它们相同则产生失败信号。还优选地提供额外的逻辑电路，其确定电路的节点是否保持在预充电状态。

4. 发明授权

US07574642B2 Multiple uses for BIST test latches 失效
标题翻译：用于BIST测试锁存器的多种用途
公开(公告)号：US07574642B2
公开(公告)日：2009-08-11
申请号：US11101615
申请日：2005-04-07
申请人： Steven Ross Ferguson , Garrett Stephen Koch , Osamu Takahashi , Michael Brian White
发明人： Steven Ross Ferguson , Garrett Stephen Koch , Osamu Takahashi , Michael Brian White
IPC分类号： G01R31/28
CPC分类号： G01R31/318544 , G01R31/318536
摘要： A method is provided to utilize built-in self test (BIST) latches for multiple purposes. Conventionally, BIST latches are single purpose. Hence, separate latches are utilized for array built-in self test (ABIST) and logic built-in self test (LBIST) operations. By having the separate latches, though, a substantial amount area is lost. Therefore, to better utilize the latches and the area, ABIST latches are reconfigured to utilize some previously unused ports to allow for multiple uses for the latches, such as for LBIST.
摘要翻译：提供了一种用于多种用途的内置自检（BIST）锁存器的方法。通常，BIST锁存器是单一目的。因此，单独的锁存器用于阵列内置自检（ABIST）和逻辑内置自检（LBIST）操作。然而，通过使用单独的锁存器，大量的区域丢失。因此，为了更好地利用锁存器和区域，ABIST锁存器被重新配置以利用一些以前未使用的端口来允许锁存器的多个使用，例如用于LBIST。

5. 发明授权

US5918003A Enhanced built-in self-test circuit and method 失效
标题翻译：增强内置自检电路及方法
公开(公告)号：US5918003A
公开(公告)日：1999-06-29
申请号：US800345
申请日：1997-02-14
申请人： Garrett Stephen Koch , Michael Richard Ouellette , Reid Allen Wistort
发明人： Garrett Stephen Koch , Michael Richard Ouellette , Reid Allen Wistort
IPC分类号： G01R31/3185 , G06F11/00
CPC分类号： G01R31/318555
摘要： An Array Built-In Self Test (ABIST) circuit places on-chip circuits such as memory arrays in a known state, then stops. In the alternative, the ABIST circuit may initialize to a particular subcycle within a pattern sequence, and repeatedly loop on the subcycle, or repeatedly loop on the entire pattern sequence.
摘要翻译：阵列内置自检（ABIST）电路将片上电路（如存储器阵列）置于已知状态，然后停止。在替代方案中，ABIST电路可以初始化到模式序列内的特定子周期，并且在子周期上重复循环，或者在整个模式序列上重复循环。

6. 发明授权

US08006153B2 Multiple uses for BIST test latches 失效
标题翻译：用于BIST测试锁存器的多种用途
公开(公告)号：US08006153B2
公开(公告)日：2011-08-23
申请号：US12197691
申请日：2008-08-25
申请人： Steven Ross Ferguson , Garrett Stephen Koch , Osamu Takahashi , Michael Brian White
发明人： Steven Ross Ferguson , Garrett Stephen Koch , Osamu Takahashi , Michael Brian White
IPC分类号： G01R31/28
CPC分类号： G01R31/318544 , G01R31/318536
摘要： A method, an apparatus, and a computer program are provided to utilize built-in self test (BIST) latches for multiple purposes. Conventionally, BIST latches are single purpose. Hence, separate latches are utilized for array built-in self test (ABIST) and logic built-in self test (LBIST) operations. By having the separate latches, though, a substantial amount area is lost. Therefore, to better utilize the latches and the area, ABIST latches are reconfigured to utilize some previously unused ports to allow for multiple uses for the latches, such as for LBIST.
摘要翻译：提供了一种方法，装置和计算机程序以利用用于多个目的的内置自检（BIST）锁存器。通常，BIST锁存器是单一目的。因此，单独的锁存器用于阵列内置自检（ABIST）和逻辑内置自检（LBIST）操作。然而，通过使用单独的锁存器，大量的区域丢失。因此，为了更好地利用锁存器和区域，ABIST锁存器被重新配置以利用一些以前未使用的端口来允许锁存器的多个使用，例如用于LBIST。

7. 发明申请

US20080313512A1 MULTIPLE USES FOR BIST TEST LATCHES 失效
标题翻译：多种用途，用于BIST测试锁
公开(公告)号：US20080313512A1
公开(公告)日：2008-12-18
申请号：US12197691
申请日：2008-08-25
申请人： Steven Ross Ferguson , Garrett Stephen Koch , Osamu Takahashi , Michael Brian White
发明人： Steven Ross Ferguson , Garrett Stephen Koch , Osamu Takahashi , Michael Brian White
IPC分类号： G01R31/3187 , G06F11/27
CPC分类号： G01R31/318544 , G01R31/318536
摘要： A method, an apparatus, and a computer program are provided to utilize built-in self test (BIST) latches for multiple purposes. Conventionally, BIST latches are single purpose. Hence, separate latches are utilized for array built-in self test (ABIST) and logic built-in self test (LBIST) operations. By having the separate latches, though, a substantial amount area is lost. Therefore, to better utilize the latches and the area, ABIST latches are reconfigured to utilize some previously unused ports to allow for multiple uses for the latches, such as for LBIST.
摘要翻译：提供了一种方法，装置和计算机程序以利用用于多个目的的内置自检（BIST）锁存器。通常，BIST锁存器是单一目的。因此，单独的锁存器用于阵列内置自检（ABIST）和逻辑内置自检（LBIST）操作。然而，通过使用单独的锁存器，大量的区域丢失。因此，为了更好地利用锁存器和区域，ABIST锁存器被重新配置以利用一些以前未使用的端口来允许锁存器的多个使用，例如用于LBIST。

8. 发明申请

US20070011978A1 Shingle With Reinforcement Layer 失效
标题翻译：加固层
公开(公告)号：US20070011978A1
公开(公告)日：2007-01-18
申请号：US11421893
申请日：2006-06-02
申请人： Husnu Kalkanoglu , Stephen Koch
发明人： Husnu Kalkanoglu , Stephen Koch
IPC分类号： E04D1/00
CPC分类号： E04D1/28 , B32B5/24 , B32B11/02 , B32B2250/02 , B32B2255/20 , B32B2260/021 , B32B2260/042 , B32B2262/101 , B32B2307/5825 , B32B2395/00 , B32B2419/06 , C09D195/00 , E04D1/20 , E04D1/22 , E04D1/26 , E04D1/34 , E04D2001/005 , E04D2001/3452 , E04D2001/3455 , E04D2001/3461 , E04D2001/3482 , Y10T156/10 , Y10T428/24372 , Y10T428/25
摘要： A shingle and a method of making it is provided in which the rear surface of the shingle is provided with an attached reinforcement layer through which fasteners may be applied when the shingle is applied to a roof.
摘要翻译：提供了一种木瓦和其制造方法，其中木瓦的后表面设置有附接的加强层，当将木瓦施加到屋顶时，可以通过该加固层施加紧固件。

9. 发明授权

US5859804A Method and apparatus for real time two dimensional redundancy allocation 失效
公开(公告)号：US5859804A
公开(公告)日：1999-01-12
申请号：US938757
申请日：1997-09-26
申请人： Erik Leigh Hedberg , Garrett Stephen Koch
发明人： Erik Leigh Hedberg , Garrett Stephen Koch
IPC分类号： G06F12/16 , G11C29/00 , G11C29/04 , G11C29/12 , G11C29/44 , G11C29/56 , G11C7/00
CPC分类号： G11C29/72 , G11C29/44
摘要： A method and apparatus are provided in an array built in self test (ABIST) environment formed on a semiconductor chip having an array of memory cells arranged in columns and rows and column and row redundant lines which includes testing the array along the columns to identify a given number of faulty cells in each of the columns, storing the column addresses having the given number of faulty cells in first registers, further testing the array along the columns or rows to identify any additional faulty cells while masking the cells having the stored column addresses and storing the row addresses having the faulty cell in second registers until all of the second registers store row addresses, and after all of the second registers store row addresses, continue testing the array while masking the cells having the stored column or row addresses and storing the column addresses of any remaining additional faulty cell in any unused register of the first registers.

10. 发明授权

US5790564A Memory array built-in self-test circuit having a programmable pattern generator for allowing unique read/write operations to adjacent memory cells, and method therefor 失效
标题翻译：具有可编程模式发生器的内存自检电路的存储器阵列，用于允许对相邻存储单元的唯一的读/写操作及其方法
公开(公告)号：US5790564A
公开(公告)日：1998-08-04
申请号：US485296
申请日：1995-06-07
申请人： Robert Dean Adams , John Connor , Garrett Stephen Koch , Luigi Ternullo, Jr.
发明人： Robert Dean Adams , John Connor , Garrett Stephen Koch , Luigi Ternullo, Jr.
IPC分类号： G11C29/12 , G11C29/10 , G11C29/36 , G01R31/28
CPC分类号： G11C29/36
摘要： An ABIST circuit for testing a memory array has a blanket write subcycle (WC), an RC3 subcycle, and an RC4 subcycle. The ABIST circuit includes a programmable pattern generator that provides eight programmable data bits, eight programmable read/write bits, and two programmable address frequency bits to determine the specific test patterns applied to the memory array. The address frequency bits determine how many memory cycles will be performed on each cell of the memory array. In X1 mode, only one memory cycle is performed on each cell during any given subcycle. In X2 mode, two memory cycles are performed on each cell, allowing a cell to be written, then subsequently read in the same subcycle. In X4 mode, four memory cycles are performed on each cell, and in X8 mode, all eight bits of read/write and data are used on each cell, resulting in eight memory cycles for each cell within the memory array.
摘要翻译：用于测试存储器阵列的ABIST电路具有毯子写入子周期（WC），RC3子周期和RC4子周期。 ABIST电路包括一个可编程模式发生器，提供八个可编程数据位，八个可编程读/写位和两个可编程地址频率位，以确定应用于存储器阵列的特定测试模式。地址频率位决定在存储器阵列的每个单元上执行多少个内存周期。在X1模式下，在任何给定的子周期内，每个单元只执行一个存储周期。在X2模式下，对每个单元执行两个存储周期，允许单元写入，然后在相同的子周期中读取。在X4模式下，对每个单元执行四个存储周期，在X8模式下，每个单元都使用8位读/写和数据，从而为存储器阵列内的每个单元提供8个存储周期。

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