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1. 发明授权

US09001568B2 Testing signal development on a bit line in an SRAM 有权
标题翻译：在SRAM中的位线测试信号开发
公开(公告)号：US09001568B2
公开(公告)日：2015-04-07
申请号：US13611863
申请日：2012-09-12
申请人： Srinivasa Raghavan Sridhara
发明人： Srinivasa Raghavan Sridhara
IPC分类号： G11C11/00 , G11C29/50 , G11C11/41
CPC分类号： G11C11/419 , G11C11/41 , G11C29/50012
摘要： An embodiment of the invention discloses a method for testing a memory cell in an SRAM. The number of dummy memory cells on a single dummy word line used to drive the dummy bit lines is selected. A binary logical value is written to a memory cell in the SRAM. The single dummy word line and a word line containing the memory cell in the SRAM are driven to logical high values concurrently. A dummy bit line, driven by the dummy memory cells, drives an input of a buffer to a binary logical value stored in the dummy memory cells. An output of the buffer enables a sense amp to amplify a voltage developed across the bit lines electrically connected to the memory cell.
摘要翻译：本发明的实施例公开了一种用于测试SRAM中的存储单元的方法。选择用于驱动虚拟位线的单个虚拟字线上的虚拟存储器单元的数量。二进制逻辑值被写入SRAM中的存储单元。单个虚拟字线和包含SRAM中的存储单元的字线被并行地驱动到逻辑高值。由虚拟存储器单元驱动的虚拟位线将缓冲器的输入驱动到存储在虚拟存储单元中的二进制逻辑值。缓冲器的输出使得读出放大器放大电连接到存储器单元的位线之间产生的电压。

2. 发明授权

US08218496B2 Random access cyclic prefix dimensioning in wireless networks 有权
标题翻译：无线网络中的随机接入循环前缀维度
公开(公告)号：US08218496B2
公开(公告)日：2012-07-10
申请号：US12252021
申请日：2008-10-15
申请人： Pierre Bertrand , Srinivasa Raghavan Sridhara
发明人： Pierre Bertrand , Srinivasa Raghavan Sridhara
IPC分类号： H04W74/02 , H04J11/00 , H04W4/00
CPC分类号： H04W74/0883 , H04L27/2613 , H04L27/2633 , H04W8/26 , H04W48/08
摘要： User equipment (UE)-initiated accesses within a cellular network include non-synchronized random access requests when the UE is not synchronized with a base station that is serving a cell occupied by the UE. The random access request is formed by generating a set of samples at a selected sample rate, such that the set of samples spans a specified duration period, wherein the sample rate is one of a plurality of different sample rates enabling different implementations of the random access transmission. The specified duration period is integrally divisible by each of the plurality of different sample periods.
摘要翻译：当UE与正在服务于UE占用的小区的基站不同步时，蜂窝网络内的用户设备（UE）引入的接入包括非同步的随机接入请求。随机存取请求是通过以选定的采样率产生一组采样而形成的，使得该组采样跨越指定的持续时间段，其中采样率是允许不同实现的随机存取的多个不同采样率之一传输。指定的持续时间段可以由多个不同的采样周期中的每一个整体地整除。

3. 发明授权

US09997255B2 Testing retention mode of an SRAM array 有权
公开(公告)号：US09997255B2
公开(公告)日：2018-06-12
申请号：US13567227
申请日：2012-08-06
申请人： Srinivasa Raghavan Sridhara
发明人： Srinivasa Raghavan Sridhara
IPC分类号： G11C7/00 , G11C29/00 , G11C29/50 , G11C11/41
CPC分类号： G11C29/00 , G11C11/41 , G11C29/50016
摘要： An embodiment of the invention discloses a method for testing the retention mode of an array of SRAM cells. A data pattern is written to the array. After the data pattern is written, a retention circuit is enabled for a period of time that drops the voltage on a supply line. During this period of time, a first current is drawn from the supply line by sources internal (i.e. leakage current) to the array. Also during this time period, current is drawn from the supply line by a discharge circuit. The second current is provided to shorten the time required to test the retention mode of the array. After the period of time has expired, the retention mode and the discharge circuit are disabled and the data pattern is read from the array and compared to the data pattern written to the array.

4. 发明申请

US20140071736A1 TESTING SIGNAL DEVELOPMENT ON A BIT LINE IN AN SRAM 有权
标题翻译：在SRAM中测试信号发生在位线上
公开(公告)号：US20140071736A1
公开(公告)日：2014-03-13
申请号：US13611863
申请日：2012-09-12
申请人： Srinivasa Raghavan Sridhara
发明人： Srinivasa Raghavan Sridhara
IPC分类号： G11C29/00 , G11C11/413
CPC分类号： G11C11/419 , G11C11/41 , G11C29/50012
摘要： An embodiment of the invention discloses a method for testing a memory cell in an SRAM. The number of dummy memory cells on a single dummy word line used to drive the dummy bit lines is selected. A binary logical value is written to a memory cell in the SRAM. The single dummy word line and a word line containing the memory cell in the SRAM are driven to logical high values concurrently. A dummy bit line, driven by the dummy memory cells, drives an input of a buffer to a binary logical value stored in the dummy memory cells. An output of the buffer enables a sense amp to amplify a voltage developed across the bit lines electrically connected to the memory cell.
摘要翻译：本发明的实施例公开了一种用于测试SRAM中的存储单元的方法。选择用于驱动虚拟位线的单个虚拟字线上的虚拟存储器单元的数量。二进制逻辑值被写入SRAM中的存储单元。单个虚拟字线和包含SRAM中的存储单元的字线被并行地驱动到逻辑高值。由虚拟存储器单元驱动的虚拟位线将缓冲器的输入驱动到存储在虚拟存储单元中的二进制逻辑值。缓冲器的输出使得读出放大器放大电连接到存储单元的位线之间产生的电压。

5. 发明授权

US09236096B2 Initializing dummy bits of an SRAM tracking circuit 有权
标题翻译：初始化SRAM跟踪电路的虚拟位
公开(公告)号：US09236096B2
公开(公告)日：2016-01-12
申请号：US13611796
申请日：2012-09-12
申请人： Srinivasa Raghavan Sridhara , Raviprakash Suryanarayana Rao
发明人： Srinivasa Raghavan Sridhara , Raviprakash Suryanarayana Rao
IPC分类号： G11C11/00 , G11C7/08 , G11C7/22 , G11C29/50 , G11C11/41
CPC分类号： G11C7/08 , G11C7/227 , G11C11/41 , G11C29/50012
摘要： An embodiment of the invention discloses a method for writing concurrently a binary logical value to one or more dummy memory cells in a dummy bit line pair. A diode is electrically connected between a power supply and the positive power supply line connected to the dummy memory cells. The binary logical value is then driven on to the dummy bit line pair. Next, one or more dummy word lines are driven to a logical high allowing selected dummy memory cells to be written with the binary logical value. After the selected dummy memory cells have been written to, the one or more dummy word lines are driven to a logical low. Next the diode is disabled by turning on a PFET connected between the power supply and the positive power supply line. Turning on the PFET also electrically connects the power supply to the positive power supply line.
摘要翻译：本发明的一个实施例公开了一种用于将二进制逻辑值同时写入虚拟位线对中的一个或多个虚拟存储器单元的方法。二极管电连接在电源和连接到虚拟存储单元的正电源线之间。然后将二进制逻辑值驱动到虚拟位线对。接下来，一个或多个虚拟字线被驱动到逻辑高，允许使用二进制逻辑值来写入所选择的虚拟存储器单元。在所选择的虚拟存储器单元已被写入之后，一个或多个虚拟字线被驱动到逻辑低电平。接下来，通过打开连接在电源和正电源线之间的PFET来禁用二极管。接通PFET也将电源与正电源线电连接。

6. 发明申请

US20140071735A1 INITIALIZING DUMMY BITS OF AN SRAM TRACKING CIRCUIT 有权
标题翻译：初始化SRAM跟踪电路的DUMMY位
公开(公告)号：US20140071735A1
公开(公告)日：2014-03-13
申请号：US13611796
申请日：2012-09-12
申请人： Srinivasa Raghavan Sridhara , Raviprakash Suryanarayana Rao
发明人： Srinivasa Raghavan Sridhara , Raviprakash Suryanarayana Rao
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C7/08 , G11C7/227 , G11C11/41 , G11C29/50012
摘要： An embodiment of the invention discloses a method for writing concurrently a binary logical value to one or more dummy memory cells in a dummy bit line pair. A diode is electrically connected between a power supply and the positive power supply line connected to the dummy memory cells. The binary logical value is then driven on to the dummy bit line pair. Next, one or more dummy word lines are driven to a logical high allowing selected dummy memory cells to be written with the binary logical value. After the selected dummy memory cells have been written to, the one or more dummy word lines are driven to a logical low. Next the diode is disabled by turning on a PFET connected between the power supply and the positive power supply line. Turning on the PFET also electrically connects the power supply to the positive power supply line.
摘要翻译：本发明的一个实施例公开了一种用于将二进制逻辑值同时写入虚拟位线对中的一个或多个虚拟存储器单元的方法。二极管电连接在电源和连接到虚拟存储单元的正电源线之间。然后将二进制逻辑值驱动到虚拟位线对。接下来，一个或多个虚拟字线被驱动到逻辑高，允许使用二进制逻辑值来写入所选择的虚拟存储器单元。在所选择的虚拟存储器单元已被写入之后，一个或多个虚拟字线被驱动到逻辑低电平。接下来，通过打开连接在电源和正电源线之间的PFET来禁用二极管。接通PFET也将电源与正电源线电连接。

7. 发明授权

US09858986B2 Integrated circuit with low power SRAM 有权
公开(公告)号：US09858986B2
公开(公告)日：2018-01-02
申请号：US12848294
申请日：2010-08-02
申请人： Theodore W. Houston , Srinivasa Raghavan Sridhara
发明人： Theodore W. Houston , Srinivasa Raghavan Sridhara
IPC分类号： G11C11/413
CPC分类号： G11C11/413
摘要： An integrated circuit containing a SRAM memory with SRAM bits optimized to have a lower minimum read voltage than the minimum write voltage. A method for reading a SRAM memory bit using a read voltage that is lower than the write voltage.

8. 发明申请

US20140036609A1 TESTING RETENTION MODE OF AN SRAM ARRAY 有权
标题翻译：测试SRAM阵列的保留模式
公开(公告)号：US20140036609A1
公开(公告)日：2014-02-06
申请号：US13567227
申请日：2012-08-06
申请人： Srinivasa Raghavan Sridhara
发明人： Srinivasa Raghavan Sridhara
IPC分类号： G11C29/00
CPC分类号： G11C29/00 , G11C11/41 , G11C29/50016
摘要： An embodiment of the invention discloses a method for testing the retention mode of an array of SRAM cells. A data pattern is written to the array. After the data pattern is written, a retention circuit is enabled for a period of time that drops the voltage on a supply line. During this period of time, a first current is drawn from the supply line by sources internal (i.e. leakage current) to the array. Also during this time period, current is drawn from the supply line by a discharge circuit. The second current is provided to shorten the time required to test the retention mode of the array. After the period of time has expired, the retention mode and the discharge circuit are disabled and the data pattern is read from the array and compared to the data pattern written to the array.
摘要翻译：本发明的实施例公开了一种用于测试SRAM单元阵列的保持模式的方法。将数据模式写入阵列。在写入数据模式之后，保持电路被使能一段时间，从而降低电源线上的电压。在这段时间内，通过源（即泄漏电流）从电源线向阵列抽出第一电流。此外，在该时间段期间，通过放电电路从电源线引出电流。提供第二电流以缩短测试阵列的保持模式所需的时间。在一段时间到期后，禁用保持模式和放电电路，并从阵列读取数据模式，并与写入阵列的数据模式进行比较。

9. 发明申请

US20120026808A1 Integrated Circuit With Low Power SRAM 有权
标题翻译：集成电路与低功耗SRAM
公开(公告)号：US20120026808A1
公开(公告)日：2012-02-02
申请号：US12848294
申请日：2010-08-02
申请人： Theodore W. Houston , Srinivasa Raghavan Sridhara
发明人： Theodore W. Houston , Srinivasa Raghavan Sridhara
IPC分类号： G11C7/00
CPC分类号： G11C11/413
摘要： An integrated circuit containing a SRAM memory with SRAM bits optimized to have a lower minimum read voltage than the minimum write voltage. A method for reading a SRAM memory bit using a read voltage that is lower than the write voltage.
摘要翻译：包含SRAM存储器的集成电路，其SRAM位优化为具有比最小写入电压更低的最小读取电压。使用低于写入电压的读取电压读取SRAM存储器位的方法。

10. 发明授权

US07817490B1 Low-power operation of static memory in a read-only mode 有权
标题翻译：静态存储器在只读模式下的低功耗操作
公开(公告)号：US07817490B1
公开(公告)日：2010-10-19
申请号：US12423378
申请日：2009-04-14
申请人： Srinivasa Raghavan Sridhara
发明人： Srinivasa Raghavan Sridhara
IPC分类号： G11C5/14 , G11C11/00
CPC分类号： G11C11/419 , G11C11/417
摘要： A static random access memory (SRAM) operable that is biased at lower power supply voltages in a read-only mode than in a read/write mode. The SRAM can be embedded within a large-scale integrated circuit, for example in combination with a microprocessor and associated circuitry. Upon system control circuitry determining that an SRAM array can be operated in a read-only mode, for example that a large number of read operations are likely to be performed prior to writing to the SRAM array, the power supply voltages applied to the SRAM array are reduced. The array power supply voltage and periphery power supply voltage can be at separate voltages and separately reduced from the read/write mode to the read-only mode. The read-only mode can be readily used for instruction cache memories, and for local instruction memories associated with an embedded microcontroller.
摘要翻译：静态随机存取存储器（SRAM）可操作成在只读模式下以比读/写模式更低的电源电压偏置。 SRAM可以嵌入在大规模集成电路中，例如与微处理器和相关联的电路组合。在系统控制电路确定可以以只读模式操作SRAM阵列的情况下，例如在写入SRAM阵列之前可能执行大量的读取操作，施加到SRAM阵列的电源电压减少了阵列电源电压和外围电源电压可以分开电压，并从读/写模式分别减少到只读模式。只读模式可以容易地用于指令高速缓冲存储器以及与嵌入式微控制器相关联的本地指令存储器。

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