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1. 发明申请

US20140114887A1 HIGH PERFORMANCE INTERCONNECT PHYSICAL LAYER 有权
标题翻译：高性能互连物理层
公开(公告)号：US20140114887A1
公开(公告)日：2014-04-24
申请号：US13976919
申请日：2013-03-15
申请人： Venkatraman Iyer , Darren S. Jue , Sitaraman V. Iyer
发明人： Venkatraman Iyer , Darren S. Jue , Sitaraman V. Iyer
IPC分类号： G06N99/00
CPC分类号： G06F13/4004 , G06F13/4221 , G06N99/005 , Y02D10/14 , Y02D10/151
摘要： A set of training sequences is generated, each training sequence to include a respective training sequence header, and the training sequence header is to be DC-balanced over the set of training sequences. The set of training sequences can be combined with electric ordered sets to form supersequences for use in such tasks as link adaptation, link state transitions, byte lock, deskew, and other tasks.
摘要翻译：生成一组训练序列，每个训练序列包括相应的训练序列头部，训练序列头部将在训练序列集合上进行DC平衡。训练序列的集合可以与电子有序集合组合以形成用于诸如链路适配，链路状态转换，字节锁定，偏斜校正和其他任务之类的任务的超序列。

2. 发明申请

US20140002183A1 APPARATUS AND METHOD FOR EXTENDING BANDWIDTH AND SUPPRESSING PHASE ERRORS IN MULTI-PHASE SIGNALS 有权
标题翻译：在多相信号中扩展带宽和抑制相位误差的装置和方法
公开(公告)号：US20140002183A1
公开(公告)日：2014-01-02
申请号：US13537638
申请日：2012-06-29
申请人： Sitaraman V. Iyer , Guluke Tong
发明人： Sitaraman V. Iyer , Guluke Tong
IPC分类号： H01L25/00
CPC分类号： H01L25/00 , H01L2924/0002 , H03F3/193 , H03F3/45183 , H03F3/607 , H03F2200/321 , H03F2200/36 , H03F2203/45702 , H01L2924/00
摘要： Described herein is an integrated circuit which comprises: a first buffer, with positive trans-conductance, to drive a first signal with first phase; and a second buffer, with negative trans-conductance, to drive a second signal with second phase, wherein the first buffer and the second buffer are cross-coupled to one another.
摘要翻译：这里描述的集成电路包括：具有正跨导的第一缓冲器，以用第一相驱动第一信号; 以及具有负的跨导电压的第二缓冲器，用于以第二相驱动第二信号，其中第一缓冲器和第二缓冲器彼此交叉耦合。

3. 发明授权

US07382197B2 Adaptive tuning circuit to maximize output signal amplitude for an amplifier 有权
标题翻译：自适应调谐电路，以最大化放大器的输出信号幅度
公开(公告)号：US07382197B2
公开(公告)日：2008-06-03
申请号：US11517885
申请日：2006-09-08
申请人： Sitaraman V. Iyer
发明人： Sitaraman V. Iyer
IPC分类号： H03F3/04
CPC分类号： H03F3/45183 , H03F3/193 , H03F2200/102 , H03F2200/451 , H03F2203/45134 , H03F2203/45332 , H03F2203/45454 , H03F2203/45634 , H03F2203/45638 , H03H11/1213 , H03H11/1291
摘要： An adaptive tuning circuit to maximize the output signal amplitude of a band-pass amplifier, comprising a control circuit to tune the peak frequency of the amplifier by monitoring the change in the output signal amplitude over two successive time sampling intervals. In some embodiments, the control circuit comprises an envelope detector and a switched capacitor circuit to provide voltages indicative of the difference in the output signal amplitude over two successive time intervals. Other embodiments are described and claimed.
摘要翻译：一种用于使带通放大器的输出信号幅度最大化的自适应调谐电路，包括通过在两个连续的时间采样间隔上监测输出信号幅度的变化来调节放大器的峰值频率的控制电路。在一些实施例中，控制电路包括包络检测器和开关电容器电路，以在两个连续的时间间隔上提供指示输出信号幅度差异的电压。描述和要求保护其他实施例。

4. 发明申请

US20140320202A1 APPARATUS AND METHOD FOR EXTENDING BANDWIDTH AND SUPRESSING PHASE ERRORS IN MULTI-PHASE SIGNALS 有权
标题翻译：在多相信号中扩展带宽和减少相位误差的装置和方法
公开(公告)号：US20140320202A1
公开(公告)日：2014-10-30
申请号：US14331023
申请日：2014-07-14
申请人： SITARAMAN V. IYER , GULUKE TONG
发明人： SITARAMAN V. IYER , GULUKE TONG
IPC分类号： H01L25/00
CPC分类号： H01L25/00 , H01L2924/0002 , H03F3/193 , H03F3/45183 , H03F3/607 , H03F2200/321 , H03F2200/36 , H03F2203/45702 , H01L2924/00
摘要： Described herein is an integrated circuit which comprises: a first buffer, with positive trans-conductance, to drive a first signal with first phase; and a second buffer, with negative trans-conductance, to drive a second signal with second phase, wherein the first buffer and the second buffer are cross-coupled to one another.
摘要翻译：这里描述的集成电路包括：具有正跨导的第一缓冲器，以用第一相驱动第一信号; 以及具有负的跨导电压的第二缓冲器，用于以第二相驱动第二信号，其中第一缓冲器和第二缓冲器彼此交叉耦合。

5. 发明授权

US08779823B2 Apparatus and method for extending bandwidth and suppressing phase errors in multi-phase signals 有权
标题翻译：用于扩展带宽并抑制多相信号中的相位误差的装置和方法
公开(公告)号：US08779823B2
公开(公告)日：2014-07-15
申请号：US13537638
申请日：2012-06-29
申请人： Sitaraman V. Iyer , Guluke Tong
发明人： Sitaraman V. Iyer , Guluke Tong
IPC分类号： H03K3/00
CPC分类号： H01L25/00 , H01L2924/0002 , H03F3/193 , H03F3/45183 , H03F3/607 , H03F2200/321 , H03F2200/36 , H03F2203/45702 , H01L2924/00
摘要： Described herein is an integrated circuit which comprises: a first buffer, with positive trans-conductance, to drive a first signal with first phase; and a second buffer, with negative trans-conductance, to drive a second signal with second phase, wherein the first buffer and the second buffer are cross-coupled to one another.
摘要翻译：这里描述的集成电路包括：具有正跨导的第一缓冲器，以用第一相驱动第一信号; 以及具有负的跨导电压的第二缓冲器，用于以第二相驱动第二信号，其中第一缓冲器和第二缓冲器彼此交叉耦合。

6. 发明申请

US20150349991A1 Method and Apparatus for Baud-Rate Timing Recovery 有权
标题翻译：波特率时序恢复方法与装置
公开(公告)号：US20150349991A1
公开(公告)日：2015-12-03
申请号：US14292743
申请日：2014-05-30
申请人： Sitaraman V. Iyer , Fulvio Spagna
发明人： Sitaraman V. Iyer , Fulvio Spagna
IPC分类号： H04L25/03
CPC分类号： H04L25/03949 , H04L7/0062 , H04L25/03146
摘要： Described is an apparatus which comprises: a Decision Feedback Equalizer (DFE); and a phase detector, operationally coupled to the DFE, to set a sampling phase based on a first post-cursor value of a composite pulse response being substantially equal to zero when the phase detector collects data bits having current bit and next bit such that value of the current bit is unequal to a value of the next bit.
摘要翻译：描述了一种装置，其包括：判决反馈均衡器（DFE）; 以及相位检测器，可操作地耦合到DFE，当相位检测器收集具有当前位和下一位的数据位时，基于复合脉冲响应的第一后标值来设置采样相位，该第一后置光标值基本上等于零，的当前位不等于下一位的值。

7. 发明申请

US20140112339A1 HIGH PERFORMANCE INTERCONNECT 有权
标题翻译：高性能互连
公开(公告)号：US20140112339A1
公开(公告)日：2014-04-24
申请号：US14060191
申请日：2013-10-22
申请人： Robert J. Safranek , Robert G. Blankenship , Venkatraman Iyer , Jeff Willey , Robert Beers , Darren S. Jue , Arvind A. Kumar , Debendra Das Sharma , Jeffrey C. Swanson , Bahaa Fahim , Vedaraman Geetha , Aaron T. Spink , Fulvio Spagna , Rahul C. Shah , Sitaraman V. Iyer , Bill Harry Nale , Abhishek Das , Simon P. Johnson , Yuvraj S. Dhillon , Yen-Cheng Liu , Raj K. Ramanujan , Robert A. Maddox , Herbert H. Hum , Ashish Gupta
发明人： Robert J. Safranek , Robert G. Blankenship , Venkatraman Iyer , Jeff Willey , Robert Beers , Darren S. Jue , Arvind A. Kumar , Debendra Das Sharma , Jeffrey C. Swanson , Bahaa Fahim , Vedaraman Geetha , Aaron T. Spink , Fulvio Spagna , Rahul C. Shah , Sitaraman V. Iyer , Bill Harry Nale , Abhishek Das , Simon P. Johnson , Yuvraj S. Dhillon , Yen-Cheng Liu , Raj K. Ramanujan , Robert A. Maddox , Herbert H. Hum , Ashish Gupta
IPC分类号： H04L12/741
CPC分类号： G06F13/22 , G06F1/3287 , G06F8/71 , G06F8/73 , G06F8/77 , G06F9/30145 , G06F9/44505 , G06F9/466 , G06F11/1004 , G06F12/0806 , G06F12/0808 , G06F12/0813 , G06F12/0815 , G06F12/0831 , G06F12/0833 , G06F13/4022 , G06F13/4068 , G06F13/4221 , G06F13/4282 , G06F13/4286 , G06F13/4291 , G06F2212/1016 , G06F2212/2542 , G06F2212/622 , H04L9/0662 , H04L12/4641 , H04L45/74 , H04L49/15 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D10/40 , Y02D10/44 , Y02D30/30
摘要： A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state
摘要翻译：物理层（PHY）耦合到将包括多个通道的串行差分链路。 PHY包括发射机和接收机，以耦合到车道数量的每个车道。耦合到每个通道的发射机被配置为将时钟嵌入到要在该通道上发送的数据，并且PHY周期性地发出阻塞链路状态（BLS）请求，以使代理进入BLS以阻止链路层飞行传输，持续时间 PHY在从包括带内复位，进入低功率状态的进入和进入部分宽度状态的组中选择的PHY相关联任务的持续时间期间利用串行差分链路

8. 发明授权

US08031764B2 Multiplexer based transmitter equalization 有权
标题翻译：基于多路复用器的发射机均衡
公开(公告)号：US08031764B2
公开(公告)日：2011-10-04
申请号：US12059755
申请日：2008-03-31
申请人： Sitaraman V. Iyer , Henry Guo
发明人： Sitaraman V. Iyer , Henry Guo
IPC分类号： H03H7/30 , H03H7/40 , H03K7/00
CPC分类号： H04L25/03885
摘要： In general, in one aspect, the disclosure describes a digital signal equalizer that includes a plurality of multiplexers. The number of multiplexers defines resolution of equalization. The plurality of multiplexers are configured in groups. The number of groups is based on number of taps, and the number of multiplexers associated with a particular group is based on equalization range for the group. The multiplexers in each group select a digital value associated with the cursor or a non-cursor tap associated with the group.
摘要翻译：通常，在一个方面，本公开描述了包括多个多路复用器的数字信号均衡器。多路复用器的数量定义了均衡的分辨率。多个多路复用器被分组配置。组的数量基于抽头数，并且与特定组相关联的多路复用器的数量基于该组的均衡范围。每组中的多路复用器选择与光标相关联的数字值或与组相关联的非光标抽头。

9. 发明申请

US20090322389A1 JITTER ATTENUATING DELAY LOCKED LOOP (DLL) USING A REGENERATIVE DELAY LINE 审中-公开
标题翻译：抖动延迟延迟锁定（DLL）使用再生延时线
公开(公告)号：US20090322389A1
公开(公告)日：2009-12-31
申请号：US12145779
申请日：2008-06-25
申请人： Guneet Singh , Roan M. Nicholson , Frank O'Mahony , Sitaraman V. Iyer
发明人： Guneet Singh , Roan M. Nicholson , Frank O'Mahony , Sitaraman V. Iyer
IPC分类号： H03L7/06 , H03H11/26
CPC分类号： H03L7/083 , H03L7/0812
摘要： In general, in one aspect, the disclosure describes a delay locked loop (DLL) with a regenerative delay line that includes a cascade of delay stages. A first delay stage includes a two-input delay device which receives a 180 degree phase shifted signal as feedback. This feedback signal configures the delay line into a regenerative amplifier, the frequency response of which has peaking or resonance at the input frequency which results in jitter filtering. The amount of regeneration is determined by relative strength of an input signal and the feedback signal. Relative strength is determined by relative size of devices receiving the signals. The resonant frequency (with or without oscillations) of the delay line may automatically be tuned to the incoming clock frequency by the DLL control loop. Each of the other delay stages may include two-input delay devices with the inputs shorted for uniformity.
摘要翻译：通常，在一方面，本公开描述了具有包括级联延迟级的再生延迟线的延迟锁定环（DLL）。第一延迟级包括接收180度相移信号作为反馈的双输入延迟装置。该反馈信号将延迟线配置为再生放大器，其频率响应在输入频率处具有峰值或谐振，导致抖动滤波。再生的量由输入信号和反馈信号的相对强度决定。相对强度取决于接收信号的设备的相对大小。延迟线的谐振频率（有或没有振荡）可以通过DLL控制环自动调谐到输入时钟频率。其他延迟级中的每一个可以包括双输入延迟器件，其中输入端为均匀性而短路。

10. 发明申请

US20090245343A1 MULTIPLEXER BASED TRANSMITTER EQUALIZATION 有权
标题翻译：基于多路复用器的发射机均衡
公开(公告)号：US20090245343A1
公开(公告)日：2009-10-01
申请号：US12059755
申请日：2008-03-31
申请人： Sitaraman V. Iyer , Henry Guo
发明人： Sitaraman V. Iyer , Henry Guo
IPC分类号： H04L27/01
CPC分类号： H04L25/03885
摘要： In general, in one aspect, the disclosure describes a digital signal equalizer that includes a plurality of multiplexers. The number of multiplexers defines resolution of equalization. The plurality of multiplexers are configured in groups. The number of groups is based on number of taps, and the number of multiplexers associated with a particular group is based on equalization range for the group. The multiplexers in each group select a digital value associated with the cursor or a non-cursor tap associated with the group.
摘要翻译：通常，在一个方面，本公开描述了包括多个多路复用器的数字信号均衡器。多路复用器的数量定义了均衡的分辨率。多个多路复用器被分组配置。组的数量基于抽头数，并且与特定组相关联的多路复用器的数量基于该组的均衡范围。每组中的多路复用器选择与光标相关联的数字值或与组相关联的非光标抽头。

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