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1. 发明授权

US4985369A Method for making self-aligned ohmic contacts 失效
标题翻译：制造自对准欧姆接触的方法
公开(公告)号：US4985369A
公开(公告)日：1991-01-15
申请号：US241814
申请日：1988-09-02
申请人： Siang P. Kwok
发明人： Siang P. Kwok
IPC分类号： H01L21/28 , H01L21/285 , H01L21/338
CPC分类号： H01L29/66871 , H01L21/28 , H01L21/28587
摘要： A method of making a semiconductor device with self-aligned ohmic contacts which exhibits substantially reduced shadowing. The gate material is covered with a layer of gate mask material. The gate mask material is selectively removed to form a gate mask having sidewalls with slope profiles of an inclination sufficient to avoid maximum shadow encroachment for subsequent material depositions. Gate mask material is characterized by the sidewalls having an angularity relative to the surface of the substrate which is at least as great as the angle of evaporative deposition of ohmic contact material from a point evaporative source to the extreme gate position on the substrate.
摘要翻译：制造具有自对准欧姆接触的半导体器件的方法，其显示出显着减小的阴影。栅极材料被一层栅极掩模材料覆盖。选择性地去除栅极掩模材料以形成具有侧壁的栅极掩模，该侧壁具有足以避免用于后续材料沉积的最大阴影侵蚀的倾斜分布。栅极掩模材料的特征在于具有相对于衬底表面的角度的侧壁，其至少与欧姆接触材料从点蒸发源到衬底上的极门位置的蒸发沉积的角度一样大。

2. 发明授权

US5403778A Limited metal reaction for contact cleaning and improved metal-to-metal antifuse contact cleaning method 失效
标题翻译：有限的金属反应用于接触清洗和改进的金属对金属反熔丝接触清洗方法
公开(公告)号：US5403778A
公开(公告)日：1995-04-04
申请号：US178208
申请日：1994-01-06
申请人： Siang P. Kwok , Shoue-Jen Wang
发明人： Siang P. Kwok , Shoue-Jen Wang
IPC分类号： H01L21/82 , H01L21/768 , H01L23/525 , H01L21/44
CPC分类号： H01L23/5252 , H01L21/76888 , H01L2924/0002
摘要： An antifuse contact (30) cleaning method and the resulting antifuse (10) uses limited-reaction Ti/.alpha.-Si contact cleaning. The method includes the steps of placing a limited-reaction metal such as Ti (22, 24, 34) at the interface of a metal (20)/.alpha.-Si (32)/metal (36) antifuse contact (30). The method is to react the thin reaction metal (22, 24, 34) at a temperature of less than approximately 450.degree. C. to remove the native interface layer of the metal (20)/.alpha.-Si (32)/metal (36) antifuse to, thereby, clean the metal (20)/.alpha.-Si (32)/metal (36) antifuse contact (30).
摘要翻译：反熔丝接触（30）清洁方法和所得到的反熔丝（10）使用有限反应的Ti /α-Si接触清洗。该方法包括以下步骤：在金属（20）/α-Si（32）/金属（36）反熔丝触点（30）的界面处放置诸如Ti（22,24,34）的限定反应金属。该方法是在小于约450℃的温度下使薄的反应金属（22,24,34）反应以除去金属（20）/α-Si（32）/金属（36）的天然界面层）反熔丝，从而清洁金属（20）/α-Si（32）/金属（36）反熔丝接触（30）。

3. 发明授权

US4863879A Method of manufacturing self-aligned GaAs MESFET 失效
标题翻译：制造自对准GaAs MESFET的方法
公开(公告)号：US4863879A
公开(公告)日：1989-09-05
申请号：US133913
申请日：1987-12-16
申请人： Siang P. Kwok
发明人： Siang P. Kwok
IPC分类号： H01L21/338
CPC分类号： H01L29/66871
摘要： A self-aligned MESFET is formed by implanting a first (channel) region in a first surface portion of a gallium arsenide substrate. A dielectric layer is formed on the surface of the substrate and portions of this layer are selectively removed, to leave a relatively thick substitutional gate mesa overlying a first surface portion of the first region and a relatively thin protective portion, contiguous with the substitutional gate, overlying a second surface portion of the first region, so that the substitutional gate has sidewalls extending above the protective portion. Sidewall spacers are formed contiguous with the sidewalls of the substitutional gate, so as to overlie surface portions of the protective portion of the dielectric layer contiguous with the substitutional gate. Ions are implanted into the substrate using the substitutional gate and the sidewall spacers as a mask, thereby forming source and drain regions in the first region. The structure is annealed and the substitutional gate and sidewall spacers are removed. A conductive gate layer is formed on the first region in place of the removed substitutional gate and apertures are formed in the reduced thickness portion of the dielectric layer to expose surface portions of the source and drain regions. Ohmic contacts are connected to the source and drain regions through the apertures.
摘要翻译：通过在砷化镓衬底的第一表面部分中注入第一（沟道）区而形成自对准MESFET。在衬底的表面上形成电介质层，并且选择性地去除该层的部分，以留下覆盖第一区域的第一表面部分的相对较厚的取代栅极台面和与取代栅极邻接的较薄的保护部分，覆盖第一区域的第二表面部分，使得取代栅极具有在保护部分上方延伸的侧壁。侧壁间隔件形成为与取代栅极的侧壁邻接，以覆盖与取代栅极相邻的电介质层的保护部分的表面部分。使用取代栅极和侧壁间隔物作为掩模将离子注入到衬底中，从而在第一区域中形成源区和漏区。将该结构退火，并且去除取代的栅极和侧壁间隔物。在第一区域上形成导电栅极层，以代替去除的取代栅极，并且在电介质层的厚度减小的部分形成孔，以暴露出源区和漏区的表面部分。欧姆接触器通过孔连接到源极和漏极区域。

4. 发明授权

US4745082A Method of making a self-aligned MESFET using a substitutional gate with side walls 失效
标题翻译：使用具有侧壁的替代栅极制造自对准MESFET的方法
公开(公告)号：US4745082A
公开(公告)日：1988-05-17
申请号：US873515
申请日：1986-06-12
申请人： Siang P. Kwok
发明人： Siang P. Kwok
IPC分类号： H01L29/812 , H01L21/265 , H01L21/324 , H01L21/338 , H01L21/306 , H01L21/24
CPC分类号： H01L29/66871 , Y10S148/053 , Y10S148/139 , Y10S148/14
摘要： A process for producing a semiconductor device includes depositing a layer of insulator material onto a supporting substrate of the type having a surface which includes a channel region below the surface thereof containing a carrier concentration of a desired conductivity type, removing selected portions of the insulator material to form a substitutional gate on the substrate surface, forming side walls bounding substitutional gate to define an effective masking area in cooperation with the substitutional gate, ion implanting a dopant into the unmasked region of the substrate, removing the side walls, annealing the resultant device, removing the substitutional gate, depositing gate metal and first and second ohmic contacts in correct positional relation to one another on the substrate, and depositing metallic interconnects in electrical communication with the ohmic contacts to produce a semiconductor device. This technique is especially useful in the production of Group III-V compound semiconductors, particularly gallium arsenide semiconductors.
摘要翻译：一种用于制造半导体器件的方法包括将绝缘体材料层沉积在具有表面的支撑基底上，该表面包括其表面下方的沟道区域，其中所述沟道区域包含所需导电类型的载流子浓度，去除绝缘体材料的选定部分在衬底表面上形成取代栅极，形成限定取代栅极的侧壁，以与取代栅极配合定义有效掩蔽区域;将掺杂剂离子注入衬底的未掩模区域，去除侧壁，退火所得器件去除所述取代栅极，在所述衬底上彼此以正确的位置关系沉积栅极金属和第一和第二欧姆触点，以及沉积与所述欧姆触点电连通以产生半导体器件的金属互连。该技术在III-V族化合物半导体，特别是砷化镓半导体的生产中特别有用。

5. 发明授权

US4396437A Selective encapsulation, controlled atmosphere annealing for III-V semiconductor device fabrication 失效
标题翻译： III-V半导体器件制造的选择性封装，受控气氛退火
公开(公告)号：US4396437A
公开(公告)日：1983-08-02
申请号：US260455
申请日：1981-05-04
申请人： Siang P. Kwok , Milton Feng , Victor K. Eu
发明人： Siang P. Kwok , Milton Feng , Victor K. Eu
IPC分类号： H01L21/324 , H01L21/265
CPC分类号： H01L21/3245
摘要： A post-ion implantation annealing technique is provided to remove implantation damage in the active region of III-V (e.g., GaAs) semiconductor devices formed in a III-V semi-insulating substrate and separated by a field region. The technique involves applying a dielectric encapsulation selectively over the device active area and annealing in a controlled reducing atmosphere which includes the Group V element (e.g., arsenic). The dielectric encapsulant over the active region permits migration of the species employed to render the substrate semi-insulating (e.g., Cr in GaAs substrates), thereby resulting in high carrier mobility in the active region. Without encapsulation, migration of the species in the field region is substantially suppressed, thereby resulting in good inter-device isolation.
摘要翻译：提供离子后注入退火技术以去除在III-V半绝缘衬底中形成并被场区域分离的III-V（例如，GaAs）半导体器件的有源区域中的注入损伤。该技术涉及在器件有源区域上选择性地施加电介质封装并在包括第V族元素（例如砷）的受控还原气氛中进行退火。有源区上的电介质密封剂允许用于使衬底半绝缘（例如，GaAs衬底中的Cr）所用的物质的迁移，从而在有源区域中导致高的载流子迁移率。没有包封，实质上抑制了场区域中的物质的迁移，从而导致良好的器件间隔离。

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