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1. 发明授权

US08787776B2 Optical receiver with monolithically integrated photodetector 失效
标题翻译：具有单片集成光电检测器的光接收器
公开(公告)号：US08787776B2
公开(公告)日：2014-07-22
申请号：US13152320
申请日：2011-06-03
申请人： Anthony Chan Carusone , Tony Shuo-Chun Kao , Hemesh Yasotharan
发明人： Anthony Chan Carusone , Tony Shuo-Chun Kao , Hemesh Yasotharan
IPC分类号： H04B10/06
CPC分类号： H04B10/6971
摘要： An optical receiver includes a photodetector for detecting incoming optical data signals and an amplifier for providing signal gain and current to voltage conversion. The detection signal generated by the photodetector may include a distortion component caused by an operating characteristic of the photodetector. A signal compensating circuit may reconstruct the received optical data signal by effectively canceling the distortion component. For this purpose, the signal compensating circuit may include a decision feedback equalizer implemented using at least one feedback filter matched to the operating characteristic of the photodetector causing the signal distortion so as to reproduce the distortion component for cancellation. Use of a control module may also configure the optical receiver in real time to account for other operating and environmental conditions of the optical receiver. Data rates in excess of 5 Gbps may be realized in monolithic CMOS photodetectors when the signal compensating circuit is properly matched.
摘要翻译：光接收器包括用于检测输入光数据信号的光电检测器和用于提供信号增益和电流到电压转换的放大器。由光检测器产生的检测信号可以包括由光电检测器的工作特性引起的失真分量。信号补偿电路可以通过有效地消除失真分量来重构所接收的光数据信号。为此，信号补偿电路可以包括使用与光电检测器的操作特性匹配的至少一个反馈滤波器来实现的判决反馈均衡器，其导致信号失真，以便再现用于消除的失真分量。控制模块的使用也可以实时配置光接收机以考虑光接收机的其它操作和环境条件。当信号补偿电路正确匹配时，单片CMOS光电探测器可实现超过5 Gbps的数据速率。

2. 发明授权

US08736334B2 Current mode logic latch 有权
标题翻译：电流模式逻辑锁存
公开(公告)号：US08736334B2
公开(公告)日：2014-05-27
申请号：US13495786
申请日：2012-06-13
申请人： Shuo-Chun Kao , Nikola Nedovic
发明人： Shuo-Chun Kao , Nikola Nedovic
IPC分类号： H03K3/356
CPC分类号： H03K3/356 , H03K3/0233 , H03K3/356043
摘要： A current mode logic latch may include a first hold stage transistor coupled at its drain terminal to the drain terminal of a first sample stage transistor. A second hold stage transistor is coupled at its drain terminal to the drain terminal of a second sample stage transistor, coupled at its gate terminal to the drain terminal of the first hold stage transistor, and coupled at its drain terminal to a gate terminal of the first hold stage transistor. A first hold stage current source is coupled to a source terminal of the first hold stage transistor. A second hold stage current source is coupled to a source terminal of the second hold stage transistor. The hold stage switch is coupled between the source terminal of the first hold stage transistor and the source terminal of the second hold stage transistor.
摘要翻译：电流模式逻辑锁存器可以包括在其漏极端子耦合到第一采样级晶体管的漏极端子的第一保持级晶体管。第二保持级晶体管在其漏极端子耦合到第二采样级晶体管的漏极端子，其栅极端子耦合到第一保持级晶体管的漏极端子，并在其漏极端子耦合到栅极端子第一级保持晶体管。第一保持级电流源耦合到第一保持级晶体管的源极端子。第二保持级电流源耦合到第二保持级晶体管的源极端。保持级开关耦合在第一保持级晶体管的源极端子和第二保持级晶体管的源极端子之间。

3. 发明申请

US20130300501A1 BANDWIDTH EXTENSION OF AN AMPLIFIER 有权
标题翻译：放大器的带宽扩展
公开(公告)号：US20130300501A1
公开(公告)日：2013-11-14
申请号：US13468769
申请日：2012-05-10
申请人： Shuo-Chun KAO , Scott MCLEOD
发明人： Shuo-Chun KAO , Scott MCLEOD
IPC分类号： H03F3/45
CPC分类号： H03F3/45246 , H03F3/3022 , H03F2203/45248
摘要： An amplifier may include a gain stage configured to convert an input voltage signal to a current signal and to amplify the input voltage signal according to a gain. The amplifier may also include a buffer stage coupled to the gain stage at an internal node. The buffer stage may be configured to convert the current signal to an output voltage signal and to buffer the current signal from the gain stage so that a frequency bandwidth of the amplifier may be approximately maintained when the gain of the gain stage is increased.
摘要翻译：放大器可以包括被配置为将输入电压信号转换为电流信号并根据增益来放大输入电压信号的增益级。放大器还可以包括在内部节点处耦合到增益级的缓冲级。缓冲级可以被配置为将电流信号转换为输出电压信号并缓冲来自增益级的电流信号，使得当增益级的增益增加时，放大器的频率带宽可以近似保持。

4. 发明申请

US20120141122A1 OPTICAL RECEIVER WITH MONOLITHICALLY INTEGRATED PHOTODETECTOR 失效
标题翻译：光学接收器与单片集成光电转换器
公开(公告)号：US20120141122A1
公开(公告)日：2012-06-07
申请号：US13152320
申请日：2011-06-03
申请人： Anthony Chan Carusone , Tony Shuo-Chun Kao , Hemesh Yasotharan
发明人： Anthony Chan Carusone , Tony Shuo-Chun Kao , Hemesh Yasotharan
IPC分类号： H04B10/08
CPC分类号： H04B10/6971
摘要： An optical receiver includes a photodetector for detecting incoming optical data signals and an amplifier for providing signal gain and current to voltage conversion. The detection signal generated by the photodetector may include a distortion component caused by an operating characteristic of the photodetector. A signal compensating circuit may reconstruct the received optical data signal by effectively canceling the distortion component. For this purpose, the signal compensating circuit may include a decision feedback equalizer implemented using at least one feedback filter matched to the operating characteristic of the photodetector causing the signal distortion so as to reproduce the distortion component for cancellation. Use of a control module may also configure the optical receiver in real time to account for other operating and environmental conditions of the optical receiver. Data rates in excess of 5 Gbps may be realized in monolithic CMOS photodetectors when the signal compensating circuit is properly matched.
摘要翻译：光接收器包括用于检测输入光数据信号的光电检测器和用于提供信号增益和电流到电压转换的放大器。由光检测器产生的检测信号可以包括由光电检测器的工作特性引起的失真分量。信号补偿电路可以通过有效地消除失真分量来重构所接收的光数据信号。为此，信号补偿电路可以包括使用与光电检测器的操作特性匹配的至少一个反馈滤波器来实现的判决反馈均衡器，其导致信号失真，以便再现用于消除的失真分量。控制模块的使用也可以实时配置光接收机以考虑光接收机的其它操作和环境条件。当信号补偿电路正确匹配时，单片CMOS光电探测器可实现超过5 Gbps的数据速率。

5. 发明授权

US09413389B2 Automatic synchronization of a transmitter 有权
标题翻译：发射机自动同步
公开(公告)号：US09413389B2
公开(公告)日：2016-08-09
申请号：US13355202
申请日：2012-01-20
申请人： Nikola Nedovic , Shuo-Chun Kao
发明人： Nikola Nedovic , Shuo-Chun Kao
IPC分类号： H03M9/00 , H04J3/06
CPC分类号： H03M9/00 , H04J3/0685
摘要： An electronic device includes a transmission module communicatively coupled to a synchronizer. The transmission module is configured to transform received data for transmission, receive a first instruction from the synchronizer, based on the instruction adjust the phase of a clock signal used to time the transformation of the received data, and send the adjusted clock signal to the synchronizer. The synchronizer is configured to receive the adjusted clock signal, receive a data signal comprising a frequency and a phase of data to be transmitted, based on the adjusted clock signal and the data signal, determine a second instruction for the transmission module, and provide the second instruction to the transmission module.
摘要翻译：电子设备包括通信地耦合到同步器的传输模块。发送模块被配置为转换接收的数据进行发送，基于指令调整用于对接收数据进行变换的时间信号的相位的指令，从同步器接收第一指令，并将调整后的时钟信号发送到同步器。同步器被配置为接收经调整的时钟信号，基于经调整的时钟信号和数据信号接收包括要发送的数据的频率和相位的数据信号，确定传输模块的第二指令，并提供传输模块的第二条指令。

6. 发明授权

US08803609B2 Bandwidth extension of an amplifier 有权
标题翻译：放大器的带宽扩展
公开(公告)号：US08803609B2
公开(公告)日：2014-08-12
申请号：US13468769
申请日：2012-05-10
申请人： Shuo-Chun Kao , Scott McLeod
发明人： Shuo-Chun Kao , Scott McLeod
IPC分类号： H03F3/45
CPC分类号： H03F3/45246 , H03F3/3022 , H03F2203/45248
摘要： An amplifier may include a gain stage configured to convert an input voltage signal to a current signal and to amplify the input voltage signal according to a gain. The amplifier may also include a buffer stage coupled to the gain stage at an internal node. The buffer stage may be configured to convert the current signal to an output voltage signal and to buffer the current signal from the gain stage so that a frequency bandwidth of the amplifier may be approximately maintained when the gain of the gain stage is increased.
摘要翻译：放大器可以包括被配置为将输入电压信号转换为电流信号并根据增益来放大输入电压信号的增益级。放大器还可以包括在内部节点处耦合到增益级的缓冲级。缓冲级可以被配置为将电流信号转换为输出电压信号并缓冲来自增益级的电流信号，使得当增益级的增益增加时，放大器的频率带宽可以近似保持。

7. 发明授权

US08797098B2 Variable gain amplifier 有权
标题翻译：可变增益放大器
公开(公告)号：US08797098B2
公开(公告)日：2014-08-05
申请号：US13477926
申请日：2012-05-22
申请人： Shuo-Chun Kao , Nikola Nedovic
发明人： Shuo-Chun Kao , Nikola Nedovic
IPC分类号： H03F3/45
CPC分类号： H03G3/00 , H03F3/45 , H03F3/45071 , H03F3/45183 , H03F3/45197 , H03F3/45206 , H03F2203/45008 , H03F2203/45372 , H03F2203/45374 , H03F2203/45562 , H03F2203/45644 , H03F2203/45702 , H03G1/0029
摘要： A method may include applying an input differential voltage to input terminals of an amplifier, a first input terminal coupled to a gate of a first transistor and a second input terminal coupled to a gate of a second transistor. The method may also include varying a gain of the amplifier by varying at least one of: a resistance of a first resistor, the first resistor coupled between a source of the first transistor and a source of the second transistor; and a resistance of a second resistor, the second resistor coupled between a source of a third transistor and a source of a fourth transistor; wherein: the third transistor is coupled at its drain to the drain of the first transistor; and the fourth transistor is coupled at its drain to the drain of the second transistor and a gate of the third transistor and coupled at its gate to the drain of the third transistor.
摘要翻译：方法可以包括将输入差分电压施加到放大器的输入端，耦合到第一晶体管的栅极的第一输入端和耦合到第二晶体管的栅极的第二输入端。该方法还可以包括通过改变以下至少一个来改变放大器的增益：第一电阻器的电阻，耦合在第一晶体管的源极和第二晶体管的源极之间的第一电阻器; 以及第二电阻器的电阻，所述第二电阻器耦合在第三晶体管的源极和第四晶体管的源极之间; 其中：所述第三晶体管在其漏极耦合到所述第一晶体管的漏极; 并且第四晶体管在其漏极耦合到第二晶体管的漏极和第三晶体管的栅极，并在其栅极处耦合到第三晶体管的漏极。

8. 发明申请

US20130335129A1 Current Mode Logic Latch 有权
标题翻译：电流模式逻辑锁存器
公开(公告)号：US20130335129A1
公开(公告)日：2013-12-19
申请号：US13495786
申请日：2012-06-13
申请人： Shuo-Chun Kao , Nikola Nedovic
发明人： Shuo-Chun Kao , Nikola Nedovic
IPC分类号： H03K3/289
CPC分类号： H03K3/356 , H03K3/0233 , H03K3/356043
摘要： A current mode logic latch may include a first hold stage transistor coupled at its drain terminal to the drain terminal of a first sample stage transistor. A second hold stage transistor is coupled at its drain terminal to the drain terminal of a second sample stage transistor, coupled at its gate terminal to the drain terminal of the first hold stage transistor, and coupled at its drain terminal to a gate terminal of the first hold stage transistor. A first hold stage current source is coupled to a source terminal of the first hold stage transistor. A second hold stage current source is coupled to a source terminal of the second hold stage transistor. The hold stage switch is coupled between the source terminal of the first hold stage transistor and the source terminal of the second hold stage transistor.
摘要翻译：电流模式逻辑锁存器可以包括在其漏极端子耦合到第一采样级晶体管的漏极端子的第一保持级晶体管。第二保持级晶体管在其漏极端子耦合到第二采样级晶体管的漏极端子，其栅极端子耦合到第一保持级晶体管的漏极端子，并在其漏极端子耦合到栅极端子第一级保持晶体管。第一保持级电流源耦合到第一保持级晶体管的源极端子。第二保持级电流源耦合到第二保持级晶体管的源极端。保持级开关耦合在第一保持级晶体管的源极端子和第二保持级晶体管的源极端子之间。

9. 发明申请

US20130314156A1 Variable Gain Amplifier 有权
标题翻译：可变增益放大器
公开(公告)号：US20130314156A1
公开(公告)日：2013-11-28
申请号：US13477926
申请日：2012-05-22
申请人： SHUO-CHUN KAO , NIKOLA NEDOVIC
发明人： SHUO-CHUN KAO , NIKOLA NEDOVIC
IPC分类号： H03G3/30 , H03F3/45
CPC分类号： H03G3/00 , H03F3/45 , H03F3/45071 , H03F3/45183 , H03F3/45197 , H03F3/45206 , H03F2203/45008 , H03F2203/45372 , H03F2203/45374 , H03F2203/45562 , H03F2203/45644 , H03F2203/45702 , H03G1/0029
摘要： A method may include applying an input differential voltage to input terminals of an amplifier, a first input terminal coupled to a gate of a first transistor and a second input terminal coupled to a gate of a second transistor. The method may also include varying a gain of the amplifier by varying at least one of: a resistance of a first resistor, the first resistor coupled between a source of the first transistor and a source of the second transistor; and a resistance of a second resistor, the second resistor coupled between a source of a third transistor and a source of a fourth transistor; wherein: the third transistor is coupled at its drain to the drain of the first transistor; and the fourth transistor is coupled at its drain to the drain of the second transistor and a gate of the third transistor and coupled at its gate to the drain of the third transistor.
摘要翻译：方法可以包括将输入差分电压施加到放大器的输入端，耦合到第一晶体管的栅极的第一输入端和耦合到第二晶体管的栅极的第二输入端。该方法还可以包括通过改变以下至少一个来改变放大器的增益：第一电阻器的电阻，耦合在第一晶体管的源极和第二晶体管的源极之间的第一电阻器; 以及第二电阻器的电阻，所述第二电阻器耦合在第三晶体管的源极和第四晶体管的源极之间; 其中：所述第三晶体管在其漏极耦合到所述第一晶体管的漏极; 并且第四晶体管在其漏极耦合到第二晶体管的漏极和第三晶体管的栅极，并在其栅极处耦合到第三晶体管的漏极。

10. 发明申请

US20130188657A1 Automatic Synchronization of a Transmitter 有权
标题翻译：发射机的自动同步
公开(公告)号：US20130188657A1
公开(公告)日：2013-07-25
申请号：US13355202
申请日：2012-01-20
申请人： Nikola Nedovic , Shuo-Chun Kao
发明人： Nikola Nedovic , Shuo-Chun Kao
IPC分类号： H04L7/04 , H04J3/06
CPC分类号： H03M9/00 , H04J3/0685
摘要： An electronic device includes a transmission module communicatively coupled to a synchronizer. The transmission module is configured to transform received data for transmission, receive a first instruction from the synchronizer, based on the instruction adjust the phase of a clock signal used to time the transformation of the received data, and send the adjusted clock signal to the synchronizer. The synchronizer is configured to receive the adjusted clock signal, receive a data signal comprising a frequency and a phase of data to be transmitted, based on the adjusted clock signal and the data signal, determine a second instruction for the transmission module, and provide the second instruction to the transmission module.
摘要翻译：电子设备包括通信地耦合到同步器的传输模块。发送模块被配置为转换接收的数据进行发送，基于指令调整用于对接收数据进行变换的时间信号的相位的指令，从同步器接收第一指令，并将调整后的时钟信号发送到同步器。同步器被配置为接收经调整的时钟信号，基于经调整的时钟信号和数据信号接收包括要发送的数据的频率和相位的数据信号，确定传输模块的第二指令，并提供传输模块的第二条指令。

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