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1. 发明申请

US20110129995A1 MULTILAYER WIRING STRUCTURE OF SEMICONDUCTOR DEVICE, METHOD OF PRODUCING SAID MULTILAYER WIRING STRUCTURE AND SEMICONDUCTOR DEVICE TO BE USED FOR RELIABILITY EVALUATION 有权
标题翻译：半导体器件的多层布线结构，生产用于可靠性评估的多层布线结构和半导体器件的制造方法
公开(公告)号：US20110129995A1
公开(公告)日：2011-06-02
申请号：US13022950
申请日：2011-02-08
申请人： Shinichi Domae , Hiroshi Masuda , Yoshiaki Kato , Kousaku Yano
发明人： Shinichi Domae , Hiroshi Masuda , Yoshiaki Kato , Kousaku Yano
IPC分类号： H01L21/4763
CPC分类号： H01L22/34 , H01L21/2855 , H01L21/28556 , H01L21/32051 , H01L21/76805 , H01L21/76838 , H01L21/76843 , H01L23/5226 , H01L23/53219 , H01L2924/0002 , H01L2924/00
摘要： A multilayer wiring structure of a semiconductor device having a stacked structure is arranged to restrain reliability degradation due to stress applied to the region of wiring between opposite upper and lower plugs. The rate of overlap of contact surface between upper plug and wiring on contact surface between lower plug and wiring, is small to the extent that no void is generated. The multilayer wiring structure is produced such that no grain boundary is contained in the region of wiring between upper and lower plugs. The difference in thermal expansion coefficient between the material of wiring and the material of upper and lower plugs, is small to the extent that no void is generated.
摘要翻译：布置具有层叠结构的半导体器件的多层布线结构，以抑制由于施加到相对的上部和下部插塞之间的布线区域的应力的可靠性降低。上插头与下插头与布线之间的接触面上的布线之间的接触面的重叠速率小，不产生空隙的程度。制造多层布线结构，使得在上部和下部插塞之间的布线区域中不包含晶界。布线材料与上，下插头材料之间的热膨胀系数差异小到不产生空隙的程度。

2. 发明申请

US20090111262A1 MULTILAYER WIRING STRUCTURE OF SEMICONDUCTOR DEVICE, METHOD OF PRODUCING SAID MULTILAYER WIRING STRUCTURE AND SEMICONDUCTOR DEVICE TO BE USED FOR RELIABILITY EVALUATION 有权
标题翻译：半导体器件的多层布线结构，生产用于可靠性评估的多层布线结构和半导体器件的制造方法
公开(公告)号：US20090111262A1
公开(公告)日：2009-04-30
申请号：US12236914
申请日：2008-09-24
申请人： Shinichi DOMAE , Hiroshi Masuda , Yoshiaki Kato , Kousaku Yano
发明人： Shinichi DOMAE , Hiroshi Masuda , Yoshiaki Kato , Kousaku Yano
IPC分类号： H01L21/02
CPC分类号： H01L22/34 , H01L21/2855 , H01L21/28556 , H01L21/32051 , H01L21/76805 , H01L21/76838 , H01L21/76843 , H01L23/5226 , H01L23/53219 , H01L2924/0002 , H01L2924/00
摘要： A multilayer wiring structure of a semiconductor device having a stacked structure is arranged to restrain reliability degradation due to stress applied to the region of wiring between opposite upper and lower plugs. The rate of overlap of contact surface between upper plug and wiring on contact surface between lower plug and wiring, is small to the extent that no void is generated. The multilayer wiring structure is produced such that no grain boundary is contained in the region of wiring between upper and lower plugs. The difference in thermal expansion coefficient between the material of wiring and the material of upper and lower plugs, is small to the extent that no void is generated.
摘要翻译：布置具有层叠结构的半导体器件的多层布线结构，以抑制由于施加到相对的上部和下部插塞之间的布线区域的应力的可靠性降低。上插头与下插头与布线之间的接触面上的布线之间的接触面的重叠速率小，不产生空隙的程度。制造多层布线结构，使得在上部和下部插塞之间的布线区域中不包含晶界。布线材料与上，下插头材料之间的热膨胀系数差异小到不产生空隙的程度。

3. 发明授权

US06252427B1 CMOS inverter and standard cell using the same 有权
标题翻译： CMOS反相器和标准电池使用相同
公开(公告)号：US06252427B1
公开(公告)日：2001-06-26
申请号：US09333048
申请日：1999-06-15
申请人： Shinichi Domae , Tetsuya Ueda
发明人： Shinichi Domae , Tetsuya Ueda
IPC分类号： H03K1920
CPC分类号： H01L27/092 , H01L2924/0002 , H01L2924/00
摘要： To prevent a void from being formed in a CMOS inverter due to electromigration. A power line 11 is connected to the source of a p-channel MOS transistor Tr1 via a first contact 12. A ground line 13 is connected to the source of an n-channel MOS transistor Tr2 via a second contact 14. One terminal of a first output signal line 15 is connected to the drain of the p-channel MOS transistor Tr1 via a third contact 16, while the other terminal thereof is connected to the drain of the n-channel MOS transistor Tr2 via a fourth contact 17. one terminal of a second output signal line 18 is connected to the fourth contact 17, while the other terminal thereof extends toward the output terminal of the inverter. A first path of an input signal line 19 is connected to the gate electrode 20 of the p-channel MOS transistor Tr1 via a fifth contact 21, while a second path thereof is connected to the gate electrode 20 of the n-channel MOS transistor Tr2 via a sixth contact 22.
摘要翻译：为了防止由于电迁移而在CMOS反相器中形成空隙。电源线11经由第一触点12连接到p沟道MOS晶体管Tr1的源极。地线13连接到n的源极通道MOS晶体管Tr2经由第二触点14.第一输出信号线15的一个端子经由第三触点16连接到p沟道MOS晶体管Tr1的漏极，而另一端连接到 n沟道MOS晶体管Tr2经由第四触点17.第二输出信号线18的一个端子连接到第四触点17，而另一端延伸到逆变器的输出端。输入信号线19的第一路径经由第五接点21连接到p沟道MOS晶体管Tr1的栅电极20，其第二路径连接到n沟道MOS晶体管Tr2的栅电极20 经由第六接触件22。

4. 发明授权

US06197685B1 Method of producing multilayer wiring device with offset axises of upper and lower plugs 失效
标题翻译：制造具有上，下插头偏移轴的多层布线装置的方法
公开(公告)号：US06197685B1
公开(公告)日：2001-03-06
申请号：US09113370
申请日：1998-07-01
申请人： Shinichi Domae , Hiroshi Masuda , Yoshiaki Kato , Kousaku Yano
发明人： Shinichi Domae , Hiroshi Masuda , Yoshiaki Kato , Kousaku Yano
IPC分类号： H01L214763
CPC分类号： H01L22/34 , H01L21/2855 , H01L21/28556 , H01L21/32051 , H01L21/76805 , H01L21/76838 , H01L21/76843 , H01L23/5226 , H01L23/53219 , H01L2924/0002 , H01L2924/00
摘要： A multilayer wiring structure of a semiconductor device having a stacked structure is arranged to restrain reliability degradation due to stress applied to the region of wiring between opposite upper and lower plugs. The rate of overlap of contact surface between upper plug and wiring on contact surface between lower plug and wiring, is small to the extent that no void is generated. The multilayer wiring structure is produced such that no grain boundary is contained in the region of wiring between upper and lower plugs. The difference in thermal expansion coefficient between the material of wiring and the material of upper and lower plugs, is small to the extent that no void is generated.
摘要翻译：布置具有层叠结构的半导体器件的多层布线结构，以抑制由于施加到相对的上部和下部插塞之间的布线区域的应力的可靠性降低。上插头与下插头与布线之间的接触面上的布线之间的接触面的重叠速率小，不产生空隙的程度。制造多层布线结构，使得在上部和下部插塞之间的布线区域中不包含晶界。布线材料与上，下插头材料之间的热膨胀系数差异小到不产生空隙的程度。

5. 发明申请

US20120280406A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20120280406A1
公开(公告)日：2012-11-08
申请号：US13493547
申请日：2012-06-11
申请人： Shinichi DOMAE
发明人： Shinichi DOMAE
IPC分类号： H01L23/52
CPC分类号： H01L25/50 , H01L21/561 , H01L21/568 , H01L24/97 , H01L25/0657 , H01L2224/16225 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2924/01029 , H01L2224/81
摘要： A semiconductor device has a three dimensional multi-chip structure including a plurality of chips stacked one on another. The three dimensional multi-chip structure includes a first chip, and a second chip being adjacent to the first chip on an upper or lower side of the first chip, and larger than the first chip. A through electrode is formed in at least one of the first chip or the second chip. The first chip is electrically connected to the second chip via the through electrode. A resin is provided on a surface of the second chip closer to the first chip in a portion of the second chip located outside the first chip.
摘要翻译：半导体器件具有包括彼此堆叠的多个芯片的三维多芯片结构。三维多芯片结构包括第一芯片和在第一芯片的上侧或下侧与第一芯片相邻的第二芯片，并且大于第一芯片。在第一芯片或第二芯片中的至少一个中形成通孔。第一芯片经由贯通电极与第二芯片电连接。在位于第一芯片外部的第二芯片的一部分中，在第二芯片的靠近第一芯片的表面上设置树脂。

6. 发明授权

US07642654B2 Multilayer wiring structure of semiconductor device, method of producing said multilayer wiring structure and semiconductor to be used for reliability evaluation 有权
标题翻译：半导体装置的多层布线结构，制造所述多层布线结构体的方法和用于可靠性评价的半导体装置
公开(公告)号：US07642654B2
公开(公告)日：2010-01-05
申请号：US12236914
申请日：2008-09-24
申请人： Shinichi Domae , Hiroshi Masuda , Yoshiaki Kato , Kousaku Yano
发明人： Shinichi Domae , Hiroshi Masuda , Yoshiaki Kato , Kousaku Yano
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L22/34 , H01L21/2855 , H01L21/28556 , H01L21/32051 , H01L21/76805 , H01L21/76838 , H01L21/76843 , H01L23/5226 , H01L23/53219 , H01L2924/0002 , H01L2924/00
摘要： A multilayer wiring structure of a semiconductor device having a stacked structure is arranged to restrain reliability degradation due to stress applied to the region of wiring between opposite upper and lower plugs. The rate of overlap of contact surface between upper plug and wiring on contact surface between lower plug and wiring, is small to the extent that no void is generated. The multilayer wiring structure is produced such that no grain boundary is contained in the region of wiring between upper and lower plugs. The difference in thermal expansion coefficient between the material of wiring and the material of upper and lower plugs, is small to the extent that no void is generated.
摘要翻译：布置具有层叠结构的半导体器件的多层布线结构，以抑制由于施加到相对的上部和下部插塞之间的布线区域的应力的可靠性降低。上插头与下插头与布线之间的接触面上的布线之间的接触面的重叠速率小，不产生空隙的程度。制造多层布线结构，使得在上部和下部插塞之间的布线区域中不包含晶界。布线材料与上，下插头材料之间的热膨胀系数差异小到不产生空隙的程度。

7. 发明授权

US06815338B2 Multilayer wiring structure of semiconductor device, method of producing said multilayer wiring structure and semiconductor device to be used for reliability evaluation 有权
公开(公告)号：US06815338B2
公开(公告)日：2004-11-09
申请号：US10443826
申请日：2003-05-23
申请人： Shinichi Domae , Hiroshi Masuda , Yoshiaki Kato , Kousaku Yano
发明人： Shinichi Domae , Hiroshi Masuda , Yoshiaki Kato , Kousaku Yano
IPC分类号： H01L214763
CPC分类号： H01L22/34 , H01L21/2855 , H01L21/28556 , H01L21/32051 , H01L21/76805 , H01L21/76838 , H01L21/76843 , H01L23/5226 , H01L23/53219 , H01L2924/0002 , H01L2924/00
摘要： A multilayer wiring structure of a semiconductor device having a stacked structure is arranged to restrain reliability degradation due to stress applied to the region of wiring between opposite upper and lower plugs. The rate of overlap of contact surface between upper plug and wiring on contact surface between lower plug and wiring, is small to the extent that no void is generated. The multilayer wiring structure is produced such that no grain boundary is contained in the region of wiring between upper and lower plugs. The difference in thermal expansion coefficient between the material of wiring and the material of upper and lower plugs, is small to the extent that no void is generated.

8. 发明授权

US08110495B2 Multilayer wiring structure of semiconductor device, method of producing said multilayer wiring structure and semiconductor device to be used for reliability evaluation 有权
标题翻译：半导体装置的多层布线结构，制造所述多层布线结构体的方法和用于可靠性评价的半导体装置
公开(公告)号：US08110495B2
公开(公告)日：2012-02-07
申请号：US13022950
申请日：2011-02-08
申请人： Shinichi Domae , Hiroshi Masuda , Yoshiaki Kato , Kousaku Yano
发明人： Shinichi Domae , Hiroshi Masuda , Yoshiaki Kato , Kousaku Yano
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L22/34 , H01L21/2855 , H01L21/28556 , H01L21/32051 , H01L21/76805 , H01L21/76838 , H01L21/76843 , H01L23/5226 , H01L23/53219 , H01L2924/0002 , H01L2924/00
摘要： A multilayer wiring structure of a semiconductor device having a stacked structure is arranged to restrain reliability degradation due to stress applied to the region of wiring between opposite upper and lower plugs. The rate of overlap of contact surface between upper plug and wiring on contact surface between lower plug and wiring, is small to the extent that no void is generated. The multilayer wiring structure is produced such that no grain boundary is contained in the region of wiring between upper and lower plugs. The difference in thermal expansion coefficient between the material of wiring and the material of upper and lower plugs, is small to the extent that no void is generated.
摘要翻译：布置具有层叠结构的半导体器件的多层布线结构，以抑制由于施加到相对的上部和下部插塞之间的布线区域的应力的可靠性降低。上插头与下插头与布线之间的接触面上的布线之间的接触面的重叠速率小，不产生空隙的程度。制造多层布线结构，使得在上部和下部插塞之间的布线区域中不包含晶界。布线材料与上，下插头材料之间的热膨胀系数差异小到不产生空隙的程度。

9. 发明申请

US20100078827A1 MULTILAYER WIRING STRUCTURE OF SEMICONDUCTOR DEVICE, METHOD OF PRODUCING SAID MULTILAYER WIRING STRUCTURE AND SEMICONDUCTOR DEVICE TO BE USED FOR RELIABILITY EVALUATION 有权
标题翻译：半导体器件的多层布线结构，生产用于可靠性评估的多层布线结构和半导体器件的制造方法
公开(公告)号：US20100078827A1
公开(公告)日：2010-04-01
申请号：US12631592
申请日：2009-12-04
申请人： Shinichi DOMAE , Hiroshi MASUDA , Yoshiaki KATO , Kousaku YANO
发明人： Shinichi DOMAE , Hiroshi MASUDA , Yoshiaki KATO , Kousaku YANO
IPC分类号： H01L23/48 , H01L21/60
CPC分类号： H01L22/34 , H01L21/2855 , H01L21/28556 , H01L21/32051 , H01L21/76805 , H01L21/76838 , H01L21/76843 , H01L23/5226 , H01L23/53219 , H01L2924/0002 , H01L2924/00
摘要： A multilayer wiring structure of a semiconductor device having a stacked structure is arranged to restrain reliability degradation due to stress applied to the region of wiring between opposite upper and lower plugs. The rate of overlap of contact surface between upper plug and wiring on contact surface between lower plug and wiring, is small to the extent that no void is generated. The multilayer wiring structure is produced such that no grain boundary is contained in the region of wiring between upper and lower plugs. The difference in thermal expansion coefficient between the material of wiring and the material of upper and lower plugs, is small to the extent that no void is generated.
摘要翻译：布置具有层叠结构的半导体器件的多层布线结构，以抑制由于施加到相对的上部和下部插塞之间的布线区域的应力的可靠性降低。上插头与下插头与布线之间的接触面上的布线之间的接触面的重叠速率小，不产生空隙的程度。制造多层布线结构，使得在上部和下部插塞之间的布线区域中不包含晶界。布线材料与上，下插头材料之间的热膨胀系数差异小到不产生空隙的程度。

10. 发明授权

US07443031B2 Multilayer wiring structure of semiconductor device, method of producing said multilayer wiring structure and semiconductor device to be used for reliability evaluation 有权
标题翻译：半导体装置的多层布线结构，制造所述多层布线结构体的方法和用于可靠性评价的半导体装置
公开(公告)号：US07443031B2
公开(公告)日：2008-10-28
申请号：US11582982
申请日：2006-10-19
申请人： Shinichi Domae , Hiroshi Masuda , Yoshiaki Kato , Kousaku Yano
发明人： Shinichi Domae , Hiroshi Masuda , Yoshiaki Kato , Kousaku Yano
IPC分类号： H01L23/48
CPC分类号： H01L22/34 , H01L21/2855 , H01L21/28556 , H01L21/32051 , H01L21/76805 , H01L21/76838 , H01L21/76843 , H01L23/5226 , H01L23/53219 , H01L2924/0002 , H01L2924/00
摘要： A multilayer wiring structure of a semiconductor device having a stacked structure is arranged to restrain reliability degradation due to stress applied to the region of wiring between opposite upper and lower plugs. The rate of overlap of contact surface between upper plug and wiring on contact surface between lower plug and wiring, is small to the extent that no void is generated. The multilayer wiring structure is produced such that no grain boundary is contained in the region of wiring between upper and lower plugs. The difference in thermal expansion coefficient between the material of wiring and the material of upper and lower plugs, is small to the extent that no void is generated.
摘要翻译：布置具有层叠结构的半导体器件的多层布线结构，以防止由于施加到相对的上部和下部插塞之间的布线区域的应力引起的可靠性降低。上插头与下插头与布线之间的接触面上的布线之间的接触面的重叠速率小，不产生空隙的程度。制造多层布线结构，使得在上部和下部插塞之间的布线区域中不包含晶界。布线材料与上，下插头材料之间的热膨胀系数差异小到不产生空隙的程度。

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