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1. 发明授权

US5341383A Circuit arrangement suitable for testing cells arranged in rows and columns, semiconductor integrated circuit device having the same, and method for arranging circuit blocks on chip 失效
标题翻译：适用于测试以行和列排列的单元的电路布置，具有该单元的半导体集成电路器件，以及用于在芯片上排列电路块的方法
公开(公告)号：US5341383A
公开(公告)日：1994-08-23
申请号：US736999
申请日：1991-07-29
申请人： Junichi Shikatani , Shigeki Kawahara
发明人： Junichi Shikatani , Shigeki Kawahara
IPC分类号： G01R31/3185 , G01R31/28
CPC分类号： G01R31/318516
摘要： A circuit arrangement formed on an IC chip includes a first type block and a second type block. The first type block has a plurality of cells arranged into rows and columns and a plurality of transistors respectively provided for the cells. Each of the transistors has a first terminal coupled to a corresponding one of the cells, a second terminal and a gate terminal. The second type block is a block which is not required to be test in a way identical to that for the first type block. A probe line driver tests the cells in the first type block, and is located along a first edge of the first type block. A plurality of probe lines extend from the probe line driver and run in the first type block. Each of the probe lines is connected to the gate of a corresponding one of the transistors. A sense circuit senses data read out from the cells via a plurality of sense lines running in the first type block. Each of the sense lines is connected to the second terminal of a corresponding one of the transistors. The sense circuit is located along a second edge of the first type block substantially perpendicular to the first edge of the first type block. A test control circuit controls the probe line driver and the sense circuit so that data are successively read out from the cells and transferred to the sense lines via the transistors. The test control circuit is adjacent to the probe line driver and the sense circuit.
摘要翻译：形成在IC芯片上的电路装置包括第一类型块和第二类型块。第一类型块具有排列成行和列的多个单元和分别为单元提供的多个晶体管。每个晶体管具有耦合到相应的一个单元的第一端子，第二端子和栅极端子。第二类型块是不需要以与第一类型块相同的方式测试的块。探针线驱动器测试第一类型块中的单元，并且沿着第一类型块的第一边缘定位。多个探针线从探针线驱动器延伸并在第一类型块中运行。每个探针线连接到相应的一个晶体管的栅极。感测电路通过在第一类型块中运行的多条感测线路感测从单元读出的数据。每个感测线连接到相应的一个晶体管的第二端子。感测电路沿着基本上垂直于第一类型块的第一边缘的第一类型块的第二边缘定位。测试控制电路控制探针线驱动器和感测电路，使得数据从单元连续地读出并通过晶体管传送到感测线。测试控制电路与探测线驱动器和感测电路相邻。

2. 发明授权

US5506162A Method of producing a semiconductor integrated circuit device using a master slice approach 失效
标题翻译：使用主切片方法制造半导体集成电路器件的方法
公开(公告)号：US5506162A
公开(公告)日：1996-04-09
申请号：US441011
申请日：1995-05-15
申请人： Yoshio Hirose , Koichi Yamashita , Shigeki Kawahara , Shinji Sato , Takeshi Sasaki , Ataru Kumagai
发明人： Yoshio Hirose , Koichi Yamashita , Shigeki Kawahara , Shinji Sato , Takeshi Sasaki , Ataru Kumagai
IPC分类号： H01L21/82 , H01L23/528 , H01L27/118 , H01L21/8238
CPC分类号： H01L23/528 , H01L21/82 , H01L27/11807 , H01L2924/0002
摘要： A semiconductor integrated circuit device provides; a master chip including a basic cell region having a plurality of basic cell arrays arranged thereon, for forming various kinds of circuits. An input/output cell region provides a plurality of input/output cells arranged along the periphery of the basic cell region. A first wiring layer is formed on the basic cell region and the input/output cell region via a first insulation layer and has contact holes at predetermined positions. The first wiring layer includes fixed wirings irrespective of the kind of circuit to be formed. A second wiring layer is formed on the first wiring layer via a second insulation layer having through holes at predetermined positions. The second wiring layer includes programmed wirings to specify the kind of circuit to be formed. Only the wiring pattern of the second wiring layer is suitably changed in accordance with the kind of circuits to be formed and connected among the input/output cell region, basic cell regions in regions corresponding to the input/output cell regions and the basic cell region, thereby greatly reducing a turnaround time of the device.
摘要翻译：一种半导体集成电路器件主芯片，其包括具有布置在其上的多个基本单元阵列的基本单元区域，用于形成各种电路。输入/输出单元区域提供沿着基本单元区域的周边布置的多个输入/输出单元。第一布线层经由第一绝缘层形成在基体单元区域和输入/输出单元区域上，并且在预定位置具有接触孔。无论形成电路的种类如何，第一布线层均包括固定布线。通过在预定位置具有通孔的第二绝缘层，在第一布线层上形成第二布线层。第二布线层包括用于指定要形成的电路的种类的编程布线。根据在输入/输出单元区域，对应于输入/输出单元区域和基本单元区域的区域中的基本单元区域之间形成和连接的电路的种类，适当地改变第二布线层的布线图案，从而大大减少了设备的周转时间。

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