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1. 发明授权

US07979681B2 System and method of selectively accessing a register file 有权
标题翻译：选择性地访问寄存器文件的系统和方法
公开(公告)号：US07979681B2
公开(公告)日：2011-07-12
申请号：US11943190
申请日：2007-11-20
申请人： Suresh K. Venkumahanti , Lucian Codrescu , Shankar Krithivasan , Jian Shen , Lin Wang
发明人： Suresh K. Venkumahanti , Lucian Codrescu , Shankar Krithivasan , Jian Shen , Lin Wang
IPC分类号： G06F9/00
CPC分类号： G06F9/30101 , G06F9/30072 , G06F9/30112 , G06F9/30141 , G06F9/3016 , G06F9/3824
摘要： In a particular embodiment, a method is disclosed that includes identifying a first block of bits within a result to be written to a destination register by an execution unit. The result includes a plurality of bits having the first block of bits and a second block of bits. The first block of bits has a value of zero. The method further includes providing an encoded bit value representing the first block of bits to a control register and selectively writing the second block of bits, but not the first block of bits, to the destination register. The destination register is sized to receive the first and second blocks of bits.
摘要翻译：在特定实施例中，公开了一种方法，其包括通过执行单元识别要写入到目的地寄存器的结果内的第一比特块。结果包括具有第一比特块和第二比特块的多个比特。第一个位块的值为零。该方法还包括向控制寄存器提供表示第一比特位的编码比特值，并将第二比特块而不是第一比特块写入目的寄存器。目的地寄存器的大小适于接收第一和第二位块。

2. 发明授权

US07877571B2 System and method of determining an address of an element within a table 有权
标题翻译：确定表中元素的地址的系统和方法
公开(公告)号：US07877571B2
公开(公告)日：2011-01-25
申请号：US11943265
申请日：2007-11-20
申请人： Shankar Krithivasan , Lucian Codrescu , Erich James Plondke , Mao Zeng
发明人： Shankar Krithivasan , Lucian Codrescu , Erich James Plondke , Mao Zeng
IPC分类号： G06F12/00
CPC分类号： G06F9/3555 , G06F9/30018 , G06F9/30032 , G06F9/3004
摘要： In a particular embodiment, a method is disclosed that includes executing a single instruction to identify a location within a table stored at a memory. The single instruction is executable by a processor to extract bit field data from a first register and insert the bit field data into an index portion of a second register. The second register includes a table address portion and an index portion. The table address portion includes a table address identifying a memory location associated with a table. The table address and the bit field data combine to form an indexed address to an element within the table.
摘要翻译：在特定实施例中，公开了一种方法，其包括执行单个指令以识别存储在存储器中的表中的位置。单个指令可由处理器执行以从第一寄存器提取位字段数据，并将位字段数据插入第二寄存器的索引部分。第二寄存器包括表地址部分和索引部分。表地址部分包括标识与表相关联的存储器位置的表地址。表地址和位字段数据组合起来，形成一个索引地址给表中的一个元素。

3. 发明申请

US20090177724A1 Processor and Method of Determining a Normalization Count 失效
标题翻译：确定规范化计数的处理器和方法
公开(公告)号：US20090177724A1
公开(公告)日：2009-07-09
申请号：US11971230
申请日：2008-01-09
申请人： Shankar Krithivasan , Erich James Plondke , Lucian Codrescu , Mao Zeng
发明人： Shankar Krithivasan , Erich James Plondke , Lucian Codrescu , Mao Zeng
IPC分类号： G06F5/01
CPC分类号： G06F7/74 , G06F7/49936
摘要： In a particular embodiment, a method is disclosed that includes receiving an operand to be normalized at a normalization logic circuit, where the operand includes a plurality of bits. The method further includes generating a zero output when a value of the operand is equal to zero and, when the value is not equal to zero, generating an output value representing a number that is one less than a count of leading bits of the operand.
摘要翻译：在特定实施例中，公开了一种方法，其包括接收在归一化逻辑电路中归一化的操作数，其中操作数包括多个位。该方法还包括当操作数的值等于零时产生零输出，并且当该值不等于零时，生成表示小于该操作数的前导位的计数的数字的输出值。

4. 发明申请

US20070192399A1 Power-efficient sign extension for booth multiplication methods and systems 有权
标题翻译：用于展台乘法方法和系统的高效符号扩展
公开(公告)号：US20070192399A1
公开(公告)日：2007-08-16
申请号：US11356359
申请日：2006-02-15
申请人： Shankar Krithivasan , Christopher Koob , William Anderson
发明人： Shankar Krithivasan , Christopher Koob , William Anderson
IPC分类号： G06F7/52
CPC分类号： G06F7/5338 , G06F7/49994 , G06F7/5443
摘要： Techniques for the design and use of a digital signal processor, including processing transmissions in a communications (e.g., CDMA) system. Power-efficient sign extension for Booth multiplication processes involves applying a sign bit in a Booth multiplication tree. The sign bit allows the Booth multiplication process to perform a sign extension step. This further involves one-extending a predetermined partial product row of the Booth multiplication tree using a sign bit for preserving the correct sign of the predetermined partial product row. The process and system resolve the signal value of the sign bit by generating a sign-extension bit in the Booth multiplication tree. The sign-extension bit is positioned in a carry-out column to extend the product of the Booth multiplication process. Then, the method and system form a final product from the Booth multiplication tree by adding the carry-out value to the sign bit positioned at least a predetermined column of the Booth multiplication tree. The result is to effectively extend the sum component of the final product with the sign and zero-extending the carry component of the final product.
摘要翻译：用于设计和使用数字信号处理器的技术，包括处理通信（例如，CDMA）系统中的传输。展位乘法过程的功率效率符号扩展涉及在展位乘法树中应用符号位。符号位允许展位乘法过程执行符号扩展步骤。这还涉及使用用于保留预定部分乘积行的正确符号的符号位来单扩展布乘除树的预定部分乘积行。该过程和系统通过在展位乘法树中生成一个符号扩展位来解析符号位的信号值。符号扩展位位于进位列中以扩展展位乘法过程的乘积。然后，方法和系统通过将进位值添加到位于布斯乘积树的至少预定列的符号位，从布斯乘积树形成最终产品。结果是有效地扩展最终产品的总和成分与符号和零扩展最终产品的进位组件。

5. 发明申请

US20060282238A1 System and method of performing two's complement operations in a digital signal processor 失效
标题翻译：在数字信号处理器中执行二进制补码操作的系统和方法
公开(公告)号：US20060282238A1
公开(公告)日：2006-12-14
申请号：US11137070
申请日：2005-05-25
申请人： Shankar Krithivasan , Christopher Koob
发明人： Shankar Krithivasan , Christopher Koob
IPC分类号： G06F17/10
CPC分类号： G06F7/509 , G06F7/544 , G06F2207/5442
摘要： A method of completing a two's complement operation includes receiving a plurality of byte values and splitting the plurality of byte values into a first portion and a second portion. Further, the method includes inputting the first portion to a first segment of a first four-to-two compressor, performing a first four-to-two compression operation on the first portion to generate a first set of results having a first row and a second row that is offset one bit from the first row, and carrying in a first value of one to complete a first two's complement operation. The method also includes inputting the second portion to a second segment of a second four-to-two compressor and adding two values of one immediately to the right of the second portion in order to carry in a second value of one to the second portion to complete a second two's complement operation.
摘要翻译：完成二进制补码操作的方法包括接收多个字节值并将多个字节值分割成第一部分和第二部分。此外，所述方法包括将第一部分输入到第一四对二压缩机的第一段，对第一部分执行第一四到二压缩操作，以产生具有第一行和第二部分的第一组结果第二行与第一行偏移一位，并携带第一个值，以完成前两个补码操作。该方法还包括将第二部分输入到第二四对二压缩机的第二部分，并且立即将第二部分的第二部分加到第二部分的右侧，以便将第二部分的第二部分加到第二部分的第二部分完成二分之二的补充操作。

6. 发明授权

US08243100B2 System and method to perform fast rotation operations 有权
标题翻译：执行快速旋转操作的系统和方法
公开(公告)号：US08243100B2
公开(公告)日：2012-08-14
申请号：US12146825
申请日：2008-06-26
申请人： Shankar Krithivasan , Erich James Plondke , Lucian Codrescu , Mao Zeng , Remi Jonathan Gurski
发明人： Shankar Krithivasan , Erich James Plondke , Lucian Codrescu , Mao Zeng , Remi Jonathan Gurski
IPC分类号： G09G5/00
CPC分类号： G06F9/30032 , G06F7/48 , G06F7/49921 , G06F7/768
摘要： Systems and methods to perform fast rotation operations are disclosed. In a particular embodiment, a method includes executing a single instruction. The method includes receiving first data indicating a first coordinate and a second coordinate, receiving a first control value that indicates a first rotation value selected from a set of ninety degree multiples, and writing output data corresponding to the first data rotated by the first rotation value.
摘要翻译：公开了执行快速旋转操作的系统和方法。在特定实施例中，一种方法包括执行单个指令。所述方法包括：接收指示第一坐标和第二坐标的第一数据，接收指示从九十度倍数的集合中选择的第一旋转值的第一控制值，以及写入与第一旋转值旋转的第一数据相对应的输出数据。

7. 发明授权

US08234319B2 System and method of performing two's complement operations in a digital signal processor 失效
标题翻译：在数字信号处理器中执行二进制补码操作的系统和方法
公开(公告)号：US08234319B2
公开(公告)日：2012-07-31
申请号：US11137070
申请日：2005-05-25
申请人： Shankar Krithivasan , Christopher Edward Koob
发明人： Shankar Krithivasan , Christopher Edward Koob
IPC分类号： G06F7/00
CPC分类号： G06F7/509 , G06F7/544 , G06F2207/5442
摘要： A method of completing a two's complement operation includes receiving a plurality of byte values and splitting the plurality of byte values into a first portion and a second portion. Further, the method includes inputting the first portion to a first segment of a first four-to-two compressor, performing a first four-to-two compression operation on the first portion to generate a first set of results having a first row and a second row that is offset one bit from the first row, and carrying in a first value of one to complete a first two's complement operation. The method also includes inputting the second portion to a second segment of a second four-to-two compressor and adding two values of one immediately to the right of the second portion in order to carry in a second value of one to the second portion to complete a second two's complement operation.
摘要翻译：完成二进制补码操作的方法包括接收多个字节值并将多个字节值分割成第一部分和第二部分。此外，所述方法包括将第一部分输入到第一四对二压缩机的第一段，对第一部分执行第一四到二压缩操作，以产生具有第一行和第二部分的第一组结果第二行与第一行偏移一位，并携带第一个值，以完成前两个补码操作。该方法还包括将第二部分输入到第二四对二压缩机的第二部分，并且立即将第二部分的第二部分加到第二部分的右侧，以便将第二部分的第二部分加到第二部分的第二部分完成二分之二的补充操作。

8. 发明授权

US08281111B2 System and method to execute a linear feedback-shift instruction 失效
标题翻译：执行线性反馈移位指令的系统和方法
公开(公告)号：US08281111B2
公开(公告)日：2012-10-02
申请号：US12236067
申请日：2008-09-23
申请人： Erich Plondke , Lucian Codrescu , Remi Gurski , Shankar Krithivasan
发明人： Erich Plondke , Lucian Codrescu , Remi Gurski , Shankar Krithivasan
IPC分类号： G06F9/305
CPC分类号： G06F9/30018 , G06F7/584 , G06F9/30003 , G06F9/30032
摘要： A system and method to execute a linear feedback-shift instruction is disclosed. In a particular embodiment the method includes executing an instruction at a processor by receiving source data and executing a bitwise logical operation on the source data and on reference data to generate intermediate data. The method further includes determining a parity value of the intermediate data, shifting the source data, and entering the parity value of the intermediate data into a data field of the shifted source data to produce resultant data.
摘要翻译：公开了一种执行线性反馈移位指令的系统和方法。在特定实施例中，该方法包括通过接收源数据并对源数据和参考数据执行逐位逻辑运算来执行处理器处的指令以产生中间数据。该方法还包括确定中间数据的奇偶校验值，移位源数据，并将中间数据的奇偶校验值输入到移位的源数据的数据字段中，以产生结果数据。

9. 发明申请

US20100077187A1 System and Method to Execute a Linear Feedback-Shift Instruction 失效
标题翻译：执行线性反馈移位指令的系统和方法
公开(公告)号：US20100077187A1
公开(公告)日：2010-03-25
申请号：US12236067
申请日：2008-09-23
申请人： Erich Plondke , Lucian Codrescu , Remi Gurski , Shankar Krithivasan
发明人： Erich Plondke , Lucian Codrescu , Remi Gurski , Shankar Krithivasan
IPC分类号： G06F9/305
CPC分类号： G06F9/30018 , G06F7/584 , G06F9/30003 , G06F9/30032
摘要： A system and method to execute a linear feedback-shift instruction is disclosed. In a particular embodiment the method includes executing an instruction at a processor by receiving source data and executing a bitwise logical operation on the source data and on reference data to generate intermediate data. The method further includes determining a parity value of the intermediate data, shifting the source data, and entering the parity value of the intermediate data into a data field of the shifted source data to produce resultant data.
摘要翻译：公开了一种执行线性反馈移位指令的系统和方法。在特定实施例中，该方法包括通过接收源数据并对源数据和参考数据执行逐位逻辑运算来执行处理器处的指令以产生中间数据。该方法还包括确定中间数据的奇偶校验值，移位源数据，并将中间数据的奇偶校验值输入到移位的源数据的数据字段中，以产生结果数据。

10. 发明申请

US20090132783A1 System and Method of Determining an Address of an Element Within a Table 有权
标题翻译：确定表内元素地址的系统和方法
公开(公告)号：US20090132783A1
公开(公告)日：2009-05-21
申请号：US11943265
申请日：2007-11-20
申请人： Shankar Krithivasan , Lucian Codrescu , Erich James Plondke , Mao Zeng
发明人： Shankar Krithivasan , Lucian Codrescu , Erich James Plondke , Mao Zeng
IPC分类号： G06F12/10
CPC分类号： G06F9/3555 , G06F9/30018 , G06F9/30032 , G06F9/3004
摘要： In a particular embodiment, a method is disclosed that includes executing a single instruction to identify a location within a table stored at a memory. The single instruction is executable by a processor to extract bit field data from a first register and insert the bit field data into an index portion of a second register. The second register includes a table address portion and an index portion. The table address portion includes a table address identifying a memory location associated with a table. The table address and the bit field data combine to form an indexed address to an element within the table.
摘要翻译：在特定实施例中，公开了一种方法，其包括执行单个指令以识别存储在存储器中的表中的位置。单个指令可由处理器执行以从第一寄存器提取位字段数据，并将位字段数据插入第二寄存器的索引部分。第二寄存器包括表地址部分和索引部分。表地址部分包括标识与表相关联的存储器位置的表地址。表地址和位字段数据组合起来，形成一个索引地址给表中的一个元素。

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