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1. 发明申请

US20120273940A1 SEMICONDUCTOR APPARATUS AND METHOD FOR FABRICATING THE SAME 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20120273940A1
公开(公告)日：2012-11-01
申请号：US13336948
申请日：2011-12-23
申请人： Seung Hee JO
发明人： Seung Hee JO
IPC分类号： H01L23/498 , H01L21/78
CPC分类号： H01L25/0657 , H01L21/76898 , H01L23/3128 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/83 , H01L24/92 , H01L24/94 , H01L25/18 , H01L2224/0401 , H01L2224/05548 , H01L2224/11462 , H01L2224/13025 , H01L2224/13082 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13188 , H01L2224/14131 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/2732 , H01L2224/29011 , H01L2224/29013 , H01L2224/29188 , H01L2224/2919 , H01L2224/30151 , H01L2224/32145 , H01L2224/48227 , H01L2224/73257 , H01L2224/80099 , H01L2224/81203 , H01L2224/81896 , H01L2224/83191 , H01L2224/8384 , H01L2224/83855 , H01L2224/9202 , H01L2225/0651 , H01L2225/06517 , H01L2225/06544 , H01L2225/06558 , H01L2225/06565 , H01L2924/00013 , H01L2924/01029 , H01L2924/01322 , H01L2924/10253 , H01L2924/12042 , H01L2924/15311 , H01L2924/15787 , H01L2924/181 , H01L2924/05442 , H01L2924/00014 , H01L2924/0665 , H01L2924/01082 , H01L2924/01047 , H01L2924/01083 , H01L2924/01051 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/3512 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor apparatus includes a first chip comprising a first bonding pad and a dielectric layer exposes a portion of the first bonding pad; a first bonding layer covering entirely or partially the first front side of the first chip, a second chip comprising a second bonding pad and a through-silicon via, and a conductive projection formed over the second bonding pad. The dielectric layer is formed on of the first chip, a second back side of the second chip is bonded to the first front side of the first chip by the medium of the first bonding layer, and the second bonding pad formed on a second front side of the second chip is coupled to the first bonding pad by the through-silicon via.
摘要翻译：半导体装置包括：第一芯片，包括第一焊盘和介电层，暴露第一焊盘的一部分; 完全或部分地覆盖第一芯片的第一前侧的第一粘合层，包括第二焊盘和穿硅通孔的第二芯片以及形成在第二焊盘上的导电突起。电介质层形成在第一芯片上，第二芯片的第二背面通过第一接合层的介质接合到第一芯片的第一前侧，并且第二焊盘形成在第二正面的第二芯片通过硅通孔耦合到第一焊盘。

2. 发明申请

US20140204681A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME 审中-公开
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US20140204681A1
公开(公告)日：2014-07-24
申请号：US13614486
申请日：2012-09-13
申请人： Seung Hee Jo
发明人： Seung Hee Jo
IPC分类号： G11C16/14
CPC分类号： G11C16/14 , G11C11/5628 , G11C16/0483 , G11C16/24 , G11C16/26
摘要： A semiconductor memory device includes strings each configured to include a drain select transistor, memory cells, and a source select transistor coupled in series between a bit line and a common source line and peripheral circuits configured to perform an operation of precharging a bit line so that the precharge level of the bit line varies depending on whether an adjacent unselected memory cell, which is adjacent to a selected memory cell, is in the program state or the erase state, by supplying a first voltage to the adjacent unselected memory cell arranged toward the drain select transistor, a second voltage to the remaining memory cells in order to turn on the remaining memory cells, and a third voltage higher than a bit line precharge voltage to the common source line and perform a read operation of supplying a read voltage lower than the second voltage to the selected memory cell, the second voltage to the remaining memory cells including the adjacent unselected memory cell, and a ground voltage to the common source line.
摘要翻译：一种半导体存储器件包括串联的每个配置成包括排列选择晶体管，存储单元和串联耦合在位线和公共源极线之间的源极选择晶体管，以及被配置为执行对位线进行预充电的操作的外围电路，位线的预充电电平根据与所选择的存储单元相邻的相邻未选择存储单元是否处于编程状态或擦除状态，通过向邻近未选择存储单元布置的相邻未选择存储单元提供第一电压而变化漏极选择晶体管，向剩余的存储单元施加第二电压，以便将剩余的存储单元导通，以及比公共源极线高的位线预充电电压的第三电压，并且执行读取电压低于对所选择的存储单元施加第二电压，向包括相邻的未选存储单元的剩余存储单元施加第二电压到公共源极线的接地电压。

3. 发明授权

US08609535B2 Semiconductor package having through electrodes that reduce leakage current and method for manufacturing the same 有权
标题翻译：具有减少漏电流的通电极的半导体封装及其制造方法
公开(公告)号：US08609535B2
公开(公告)日：2013-12-17
申请号：US13286376
申请日：2011-11-01
申请人： Seung Hee Jo , Sung Cheol Kim , Sung Min Kim
发明人： Seung Hee Jo , Sung Cheol Kim , Sung Min Kim
IPC分类号： H01L21/283
CPC分类号： H01L25/0657 , H01L21/76898 , H01L23/3128 , H01L25/50 , H01L2224/16 , H01L2225/06513 , H01L2225/06541 , H01L2924/15311
摘要： A stacked semiconductor package having through electrodes that exhibit a reduced leakage current and a method of making the same are presented. The stacked semiconductor package includes a semiconductor chip, through-holes, and a current leakage prevention layer. The semiconductor chip has opposing first and second surfaces. The through-holes pass entirely through the semiconductor chip and are exposed at the first and second surfaces. A polarized part is formed on at least one of the first and second surfaces of the semiconductor chip. The through-electrodes are disposed within the through-holes. The current leakage prevention layer covers the polarized part and exposes ends of the through-electrodes.
摘要翻译：本发明提供一种具有通过电极显示泄漏电流减小的叠层半导体封装及其制造方法。叠层半导体封装包括半导体芯片，通孔和防止漏电流层。半导体芯片具有相对的第一和第二表面。通孔完全穿过半导体芯片，并在第一和第二表面露出。偏振部分形成在半导体芯片的第一和第二表面中的至少一个上。通孔设置在通孔内。电流防漏层覆盖极化部分并暴露通孔的端部。

4. 发明申请

US20130292818A1 SEMICONDUCTOR CHIP, SEMICONDUCTOR PACKAGE HAVING THE SAME, AND STACKED SEMICONDUCTOR PACKAGE USING THE SEMICONDUCTOR PACKAGE 审中-公开
标题翻译：半导体芯片，具有该半导体芯片的半导体封装以及使用半导体封装的堆叠半导体封装
公开(公告)号：US20130292818A1
公开(公告)日：2013-11-07
申请号：US13614869
申请日：2012-09-13
申请人： Seung Hee JO
发明人： Seung Hee JO
IPC分类号： H01L23/48
CPC分类号： H01L24/11 , H01L23/3128 , H01L24/05 , H01L24/13 , H01L24/16 , H01L25/0657 , H01L2224/0401 , H01L2224/05009 , H01L2224/05026 , H01L2224/05572 , H01L2224/05647 , H01L2224/1146 , H01L2224/13025 , H01L2224/13076 , H01L2224/13147 , H01L2224/1319 , H01L2224/1356 , H01L2224/1357 , H01L2224/13647 , H01L2224/14181 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16235 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/81193 , H01L2225/06513 , H01L2225/06541 , H01L2225/06565 , H01L2924/00014 , H01L2924/07802 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/05552
摘要： A semiconductor package includes a semiconductor chip having a front surface and a back surface; through electrode formed in the semiconductor chip to pass through the front surface and the back surface and having a first end which is disposed on the front surface and a second end which is disposed on the back surface; and back-side bump formed over the second end of the through electrode and including an embedded pattern which is formed over a portion of the second end of the through electrode and a conductive pattern which is formed over the embedded pattern and a remaining portion of the second end of the through is electrode and having a convex sectional shape.
摘要翻译：半导体封装包括具有前表面和后表面的半导体芯片; 在半导体芯片中形成的贯通电极穿过前表面和后表面，并且具有设置在前表面上的第一端和设置在后表面上的第二端; 以及在所述贯通电极的第二端上形成的背面凸起，并且包括形成在所述通孔的第二端的一部分上的嵌入图案和形成在所述嵌入图案上的导电图案，通孔的第二端是电极并且具有凸形的截面形状。

5. 发明申请

US20120045895A1 SEMICONDUCTOR PACKAGE HAVING THROUGH ELECTRODES THAT REDUCE LEAKAGE CURRENT AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：具有降低泄漏电流的电极的半导体封装及其制造方法
公开(公告)号：US20120045895A1
公开(公告)日：2012-02-23
申请号：US13286376
申请日：2011-11-01
申请人： Seung Hee JO , Sung Cheol KIM , Sung Min KIM
发明人： Seung Hee JO , Sung Cheol KIM , Sung Min KIM
IPC分类号： H01L21/283
CPC分类号： H01L25/0657 , H01L21/76898 , H01L23/3128 , H01L25/50 , H01L2224/16 , H01L2225/06513 , H01L2225/06541 , H01L2924/15311
摘要： A stacked semiconductor package having through electrodes that exhibit a reduced leakage current and a method of making the same are presented. The stacked semiconductor package includes a semiconductor chip, through-holes, and a current leakage prevention layer. The semiconductor chip has opposing first and second surfaces. The through-holes pass entirely through the semiconductor chip and are exposed at the first and second surfaces. A polarized part is formed on at least one of the first and second surfaces of the semiconductor chip. The through-electrodes are disposed within the through-holes. The current leakage prevention layer covers the polarized part and exposes ends of the through-electrodes.
摘要翻译：本发明提供一种具有通过电极显示泄漏电流减小的叠层半导体封装及其制造方法。叠层半导体封装包括半导体芯片，通孔和防止漏电流层。半导体芯片具有相对的第一和第二表面。通孔完全穿过半导体芯片，并在第一和第二表面露出。偏振部分形成在半导体芯片的第一和第二表面中的至少一个上。通孔设置在通孔内。电流防漏层覆盖极化部分并暴露通孔的端部。

6. 发明申请

US20110031609A1 SEMICONDUCTOR PACKAGE HAVING THROUGH ELECTRODES THAT REDUCE LEAKAGE CURRENT AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：具有降低泄漏电流的电极的半导体封装及其制造方法
公开(公告)号：US20110031609A1
公开(公告)日：2011-02-10
申请号：US12640102
申请日：2009-12-17
申请人： Seung Hee JO , Sung Cheol KIM , Sung Min KIM
发明人： Seung Hee JO , Sung Cheol KIM , Sung Min KIM
IPC分类号： H01L23/52 , H01L21/44
CPC分类号： H01L25/0657 , H01L21/76898 , H01L23/3128 , H01L25/50 , H01L2224/16 , H01L2225/06513 , H01L2225/06541 , H01L2924/15311
摘要： A stacked semiconductor package having through electrodes that exhibit a reduced leakage current and a method of making the same are presented. The stacked semiconductor package includes a semiconductor chip, through-holes, and a current leakage prevention layer. The semiconductor chip has opposing first and second surfaces. The through-holes pass entirely through the semiconductor chip and are exposed at the first and second surfaces. A polarized part is formed on at least one of the first and second surfaces of the semiconductor chip. The through-electrodes are disposed within the through-holes. The current leakage prevention layer covers the polarized part and exposes ends of the through-electrodes.
摘要翻译：本发明提供一种具有通过电极显示泄漏电流减小的叠层半导体封装及其制造方法。叠层半导体封装包括半导体芯片，通孔和防止漏电流层。半导体芯片具有相对的第一和第二表面。通孔完全穿过半导体芯片，并在第一和第二表面露出。偏振部分形成在半导体芯片的第一和第二表面中的至少一个上。通孔设置在通孔内。电流防漏层覆盖极化部分并暴露通孔的端部。

7. 发明授权

US08592952B2 Semiconductor chip and semiconductor package with stack chip structure 失效
标题翻译：半导体芯片和半导体封装具有堆叠芯片结构
公开(公告)号：US08592952B2
公开(公告)日：2013-11-26
申请号：US13096338
申请日：2011-04-28
申请人： Seung Hee Jo , Seong Cheol Kim
发明人： Seung Hee Jo , Seong Cheol Kim
IPC分类号： H01L29/40
CPC分类号： H01L25/0657 , H01L23/3107 , H01L23/481 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/81 , H01L24/83 , H01L25/50 , H01L2223/54426 , H01L2223/5446 , H01L2224/0401 , H01L2224/05009 , H01L2224/10165 , H01L2224/13009 , H01L2224/16146 , H01L2224/16238 , H01L2224/32146 , H01L2224/32225 , H01L2224/73204 , H01L2224/8113 , H01L2224/81132 , H01L2224/81201 , H01L2224/81903 , H01L2224/831 , H01L2225/06513 , H01L2225/06541 , H01L2225/06593 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/014 , H01L2924/14 , H01L2924/00
摘要： A semiconductor chip and semiconductor package with stack chip structure include align patterns. The align patterns are formed of magnetic materials having opposite polarities on the top and bottom of the semiconductor chip. Thus, when the plurality of chips are stacked on the substrate in order for the packaging, the semiconductor chips may be exactly aligned by the magnetic force between the align patterns of the vertically stacked chips. The semiconductor package includes a plurality of stacked semiconductor chips and a filling material. Each of the stacked semiconductor chips includes a semiconductor substrate having a first surface and a second surface, wherein a circuit pattern such as a bonding pad is formed on the first surface, and a first align pattern formed on the first surface of the semiconductor substrate, wherein the first align pattern is formed of a magnetic material.
摘要翻译：具有堆叠芯片结构的半导体芯片和半导体封装包括对准图案。对准图案由在半导体芯片的顶部和底部具有相反极性的磁性材料形成。因此，当为了包装而将多个芯片堆叠在基板上时，半导体芯片可以通过垂直堆叠的芯片的对准图案之间的磁力精确对准。半导体封装包括多个堆叠的半导体芯片和填充材料。堆叠的半导体芯片中的每一个包括具有第一表面和第二表面的半导体衬底，其中在第一表面上形成诸如焊盘的电路图案，以及形成在半导体衬底的第一表面上的第一对准图案，其中所述第一对准图案由磁性材料形成。

8. 发明申请

US20120129341A1 METHOD FOR FABRICATING VIA HOLE AND THROUGH-SILICON VIA 审中-公开
标题翻译：通过孔和通过硅制造的方法
公开(公告)号：US20120129341A1
公开(公告)日：2012-05-24
申请号：US13187845
申请日：2011-07-21
申请人： Seung Hee JO , Seong Cheol KIM
发明人： Seung Hee JO , Seong Cheol KIM
IPC分类号： H01L21/28 , H01L21/311
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a via hole includes forming a first mask pattern on a first surface of a wafer exposing a portion of the first surface of the wafer, forming a passivation region within the wafer by implanting impurities into the exposed portion of the wafer using the first mask pattern as an ion implantation barrier layer, forming an etching stop layer on the first surface of the wafer including the passivation regions, forming a second mask pattern on a second surface of the wafer faces away from the first surface of the wafer, wherein the second mask pattern exposes a portion of the second surface of the wafer over an area between the passivation regions, and forming a via hole by etching the wafer using the second mask pattern as an etching mask.
摘要翻译：一种用于制造通孔的方法包括在晶片的第一表面上形成第一掩模图案，该第一表面露出晶片的第一表面的一部分，通过将晶体中的杂质注入到晶片的暴露部分中，通过使用第一掩模图案作为离子注入阻挡层，在包括钝化区的晶片的第一表面上形成蚀刻停止层，在晶片的第二表面上形成第二掩模图案，远离晶片的第一表面，其中第二掩模图案将晶片的第二表面的一部分暴露在钝化区之间的区域上，并且使用第二掩模图案作为蚀刻掩模通过蚀刻晶片形成通孔。

9. 发明申请

US20110291246A1 SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE WITH STACK CHIP STRUCTURE 失效
标题翻译：半导体芯片和半导体封装与堆叠芯片结构
公开(公告)号：US20110291246A1
公开(公告)日：2011-12-01
申请号：US13096338
申请日：2011-04-28
申请人： Seung Hee JO , Seong Cheol KIM
发明人： Seung Hee JO , Seong Cheol KIM
IPC分类号： H01L25/07 , H01L23/492
CPC分类号： H01L25/0657 , H01L23/3107 , H01L23/481 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/81 , H01L24/83 , H01L25/50 , H01L2223/54426 , H01L2223/5446 , H01L2224/0401 , H01L2224/05009 , H01L2224/10165 , H01L2224/13009 , H01L2224/16146 , H01L2224/16238 , H01L2224/32146 , H01L2224/32225 , H01L2224/73204 , H01L2224/8113 , H01L2224/81132 , H01L2224/81201 , H01L2224/81903 , H01L2224/831 , H01L2225/06513 , H01L2225/06541 , H01L2225/06593 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/014 , H01L2924/14 , H01L2924/00
摘要： A semiconductor package includes a plurality of stacked semiconductor chips and a filling material. Each of the stacked semiconductor chips includes a semiconductor substrate having a first surface and a second surface, wherein a circuit pattern such as a bonding pad is formed on the first surface, and a first align pattern formed on the first surface of the semiconductor substrate, wherein the first align pattern is formed of a magnetic material. The filling material fills a gap between the semiconductor chips.
摘要翻译：半导体封装包括多个堆叠的半导体芯片和填充材料。堆叠的半导体芯片中的每一个包括具有第一表面和第二表面的半导体衬底，其中在第一表面上形成诸如焊盘的电路图案，以及形成在半导体衬底的第一表面上的第一对准图案，其中所述第一对准图案由磁性材料形成。填充材料填充半导体芯片之间的间隙。

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