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    • 8. 发明授权
    • Semiconductor memory device capable of easily performing delay locking operation under high frequency system clock
    • 半导体存储器件能够在高频系统时钟下容易地执行延迟锁定操作
    • US07956659B2
    • 2011-06-07
    • US11647645
    • 2006-12-29
    • Min-Young YouSeong-Jun Lee
    • Min-Young YouSeong-Jun Lee
    • H03L7/00
    • H03L7/0812G06F1/04G11C7/22G11C7/222H03K5/1565
    • A semiconductor memory device includes a first clock buffer for outputting a first internal clock signal in response to an inverted signal of the system clock signal and for correcting a duty cycle ratio of the first internal clock signal in response to a control signal; a second clock buffer for outputting a second internal clock signal in response to the system clock signal and for correcting a duty cycle ratio of the second internal clock signal in response to the control signal; an analog duty cycle correction circuit for outputting the control signal corresponding to the duty cycle ratio of the first and second internal clock signals; a mixing circuit for mixing the first and second internal clock signals and for outputting a third internal clock signal whose duty cycle is corrected; and a DLL circuit for outputting a delay-locked clock signal by using the third internal clock signal.
    • 半导体存储器件包括:第一时钟缓冲器,用于响应于系统时钟信号的反相信号输出第一内部时钟信号,并用于响应于控制信号来校正第一内部时钟信号的占空比; 第二时钟缓冲器,用于响应于所述系统时钟信号输出第二内部时钟信号,并用于响应于所述控制信号来校正所述第二内部时钟信号的占空比; 模拟占空比校正电路,用于输出对应于第一和第二内部时钟信号的占空比的控制信号; 混合电路,用于混合第一和第二内部时钟信号,并输出其占空比被校正的第三内部时钟信号; 以及DLL电路,用于通过使用第三内部时钟信号输出延迟锁定时钟信号。