专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07995390B2 NAND flash memory array with cut-off gate line and methods for operating and fabricating the same 有权
标题翻译：具有截止栅极线的NAND闪存阵列及其操作和制造方法
公开(公告)号：US07995390B2
公开(公告)日：2011-08-09
申请号：US12361107
申请日：2009-01-28
申请人： Byung-Gook Park , Seong Jae Cho
发明人： Byung-Gook Park , Seong Jae Cho
IPC分类号： G11C16/04
CPC分类号： G11C8/14 , G11C16/0483 , H01L21/26586 , H01L27/11565 , H01L27/11568 , H01L27/11582 , H01L29/66833
摘要： A NAND flash memory array, an operating method and a fabricating method of the same are provided. The NAND flash memory array has a cut-off gate line under a control gate in order to operate two cells having vertical channels independently with one control gate (i.e., a shared word line). The memory cell area is reduced considerably compared to the conventional vertical channel structure, and is better for high integration. A shared cut-off gate turn off is made during a programming operation and prevents programming the opposite cell by a self-boosting effect. It is possible to shield electrically with a shared word line (a control gate) during a reading operation, and minimizes the effect of storage condition of the opposite cell. Also, the NAND flash memory array can be fabricated by using the conventional CMOS process.
摘要翻译：提供NAND闪存阵列，其操作方法及其制造方法。 NAND闪速存储器阵列在控制栅极下方具有截止栅极线，以便利用一个控制栅极（即共享字线）独立地操作具有垂直沟道的两个单元。与传统的垂直通道结构相比，存储单元面积显着减小，并且更好地用于高集成度。共享截止门在编程操作期间关闭，并防止通过自增强效应对相对的单元进行编程。在读取操作期间可以用共享字线（控制门）进行电屏蔽，并且使对置单元的存储条件的影响最小化。而且，NAND闪存阵列可以通过使用传统的CMOS工艺来制造。

2. 发明授权

US08394698B2 NAND flash memory array with cut-off gate line and methods for operating and fabricating the same 有权
标题翻译：具有截止栅极线的NAND闪存阵列及其操作和制造方法
公开(公告)号：US08394698B2
公开(公告)日：2013-03-12
申请号：US13170533
申请日：2011-06-28
申请人： Byung-Gook Park , Seong Jae Cho
发明人： Byung-Gook Park , Seong Jae Cho
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： G11C8/14 , G11C16/0483 , H01L21/26586 , H01L27/11565 , H01L27/11568 , H01L27/11582 , H01L29/66833
摘要： A NAND flash memory array, an operating method and a fabricating method of the same are provided. The NAND flash memory array has a cut-off gate line under a control gate in order to operate two cells having vertical channels independently with one control gate (i.e., a shared word line). The memory cell area is reduced considerably compared to the conventional vertical channel structure, and is better for high integration. A shared cut-off gate turn off is made during a programming operation and prevents programming the opposite cell by a self-boosting effect. It is possible to shield electrically with a shared word line (a control gate) during a reading operation, and minimizes the effect of storage condition of the opposite cell. Also, the NAND flash memory array can be fabricated by using the conventional CMOS process.
摘要翻译：提供NAND闪存阵列，其操作方法及其制造方法。 NAND闪速存储器阵列在控制栅极下方具有截止栅极线，以便利用一个控制栅极（即共享字线）独立地操作具有垂直沟道的两个单元。与传统的垂直通道结构相比，存储单元面积显着减小，并且更好地用于高集成度。共享截止门在编程操作期间关闭，并防止通过自增强效应对相对的单元进行编程。在读取操作期间可以用共享字线（控制门）进行电屏蔽，并且使对置单元的存储条件的影响最小化。而且，NAND闪存阵列可以通过使用传统的CMOS工艺来制造。

3. 发明申请

US20080296659A1 Nand Flash Memory Array Having Pillar Structure and Fabricating Method of the Same 审中-公开
标题翻译：具有支柱结构和制造方法的Nand闪存阵列
公开(公告)号：US20080296659A1
公开(公告)日：2008-12-04
申请号：US11629601
申请日：2006-11-07
申请人： Byung Gook Park , Seong Jae Cho
发明人： Byung Gook Park , Seong Jae Cho
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： The present invention relates to a NAND flash memory array having vertical channels and sidewall gate structure and a fabricating method of the same. A NAND flash memory array of the present invention has insulator strip structure and one or more semiconductor strips are next to the both sides of the insulator strip. A NAND flash memory array of the present invention allows for an improvement of the integrity by decreasing the memory cell area by half and less, and solves the problems of the conventional three-dimensional structure regarding isolation between not only channels but also source/drain regions at the bottom of trenches. A method for fabricating the NAND flash memory array having a pillar structure, which uses the conventional CMOS process and an etching process with minimum masks, enables to cut down costs.
摘要翻译：本发明涉及具有垂直通道和侧壁栅极结构的NAND快闪存储器阵列及其制造方法。本发明的NAND闪速存储器阵列具有绝缘体带结构，并且一个或多个半导体条紧邻绝缘体条的两侧。本发明的NAND闪速存储器阵列允许通过将存储单元面积减少一半或更少来提高整体性，并且解决了传统的三维结构关于不仅通道之间的隔离的问题，而且解决了源/漏区在沟渠的底部。制造具有柱结构的NAND快闪存储器阵列的方法，其使用传统的CMOS工艺和具有最小掩模的蚀刻工艺，能够降低成本。

4. 发明授权

US5034820A Channel display circuit for distinguishing the existence or nonexistence of the signal at a satellite-broadcast receiver 失效
标题翻译：通道显示电路，用于区分卫星广播接收机处的信号的存在或不存在
公开(公告)号：US5034820A
公开(公告)日：1991-07-23
申请号：US375538
申请日：1989-07-03
申请人： Seong-Jae Cho
发明人： Seong-Jae Cho
IPC分类号： H03J1/00 , H04N5/50 , H04N7/20
CPC分类号： H03J1/0016 , H04N5/50 , H04N7/20
摘要： A circuit for distinguishing the existence or non-existence of a signal at a satellite-broadcast receiver. The circuit includes an antenna adjusting part aimed toward the satellite after the satellite signal is tuned using a channel tuning stage driven by the output of a microcomputer. The level of the IF signal is detected by the IF signal AGC amplifier and the IF signal level detector. A video signal detecting stage detects the FM signal of the IF signal AGC amplifier output and the existence or nonexistence of the video signal is determined after audio/video signal processsing, and a channel displaying means, wherein the state of said video detecting part and the antenna position where video signal exists are displayed by on-sceen operations.
摘要翻译：用于区分卫星广播接收机处的信号的存在或不存在的电路。使用由微计算机的输出驱动的信道调谐级，在卫星信号调谐之后，电路包括瞄准卫星的天线调整部。 IF信号的电平由IF信号AGC放大器和IF信号电平检测器检测。视频信号检测级检测IF信号AGC放大器输出的FM信号，并且在音频/视频信号处理之后确定视频信号的存在或不存在，以及频道显示装置，其中所述视频检测部分和视频信号存在的天线位置通过操作显示。

5. 发明申请

US20120058619A1 NAND FLASH MEMORY ARRAY HAVING PILLAR STRUCTURE AND FABRICATING METHOD OF THE SAME 有权
标题翻译：具有支柱结构的NAND闪存阵列及其制造方法
公开(公告)号：US20120058619A1
公开(公告)日：2012-03-08
申请号：US13222246
申请日：2011-08-31
申请人： Byung Gook Park , Seong Jae Cho
发明人： Byung Gook Park , Seong Jae Cho
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A method is provided for fabricating a NAND flash memory array having vertical channels and sidewall gate structure and a fabricating method of the same. The NAND flash memory array has insulator strip structure and one or more semiconductor strips are next to the both sides of the insulator strip. The NAND flash memory array allows for an improvement of the integrity by decreasing the memory cell area by half and less, and solves the problems of the conventional three-dimensional structure regarding isolation between not only channels but also source/drain regions at the bottom of trenches. The method for fabricating the NAND flash memory array having a pillar structure uses the conventional CMOS process and an etching process with minimum masks, enables to cut down costs.
摘要翻译：提供了一种用于制造具有垂直沟道和侧壁栅极结构的NAND快闪存储器阵列的方法及其制造方法。 NAND闪存阵列具有绝缘体带结构，并且一个或多个半导体条紧邻绝缘体条的两侧。 NAND闪存阵列允许通过将存储器单元面积减小一半或更少来提高整体性，并且解决了传统的三维结构关于不仅仅是通道之间的隔离的问题，而且解决了底部的源极/漏极区域沟渠制造具有柱状结构的NAND快闪存储器阵列的方法使用传统的CMOS工艺和具有最小掩模的蚀刻工艺，能够降低成本。

6. 发明授权

US5696498A Address encoding method and address decoding circuit therefor 失效
标题翻译：地址编码方式及地址解码电路
公开(公告)号：US5696498A
公开(公告)日：1997-12-09
申请号：US937751
申请日：1992-09-01
申请人： Jun Ho Lee , Seong Jae Cho
发明人： Jun Ho Lee , Seong Jae Cho
IPC分类号： H03M7/00 , G11C8/10 , H03K3/00
CPC分类号： G11C8/10
摘要： An address encoding method and an address decoding circuit therefor is disclosed. In the address encoding method, a part of the outputs of address latches are made to designate circuits to be controlled, and the rest of the outputs are made to designate the relevant addresses of the circuits to be controlled. Based on this method, the constitution of the decoding circuit becomes simple.
摘要翻译：公开了一种地址编码方法及其地址解码电路。在地址编码方法中，地址锁存器的输出的一部分被指定为要被控制的电路，其余的输出被指定为要被控制的电路的相关地址。基于该方法，解码电路的结构变得简单。

7. 发明授权

US5113086A Polarotator pulse generator circuit for a receiver of satellite broadcasting 失效
标题翻译：用于卫星广播接收机的极化器脉冲发生器电路
公开(公告)号：US5113086A
公开(公告)日：1992-05-12
申请号：US524916
申请日：1990-05-18
申请人： Seong-Jae Cho
发明人： Seong-Jae Cho
IPC分类号： H01Q1/24 , H04B7/185
CPC分类号： H04B7/185 , H01Q1/247
摘要： A polarotator pulse generator circuit is disclosed in which a sine-to-square converter converts a sine wave of AC power supply to a square wave, a clock synchronizer synchronizes the square ware of the sine-to-square converter with a high frequency clock and provides a loading instance control signal, a latch provides after synchronizing the data corresponding to the pulse width for the control of the polarotator with a clock being applied, a counter counts the clock with a start value determined by the data provided from the latch in accordance with an applied clock and loaded in accordance with the loading instance control signal, and a counter disable part stops the count until the next loading signal enters when a carry over occurs.
摘要翻译：公开了一种波导旋转器脉冲发生器电路，其中正弦平方变换器将交流电源的正弦波转换成方波，时钟同步器使正弦转换器的平方与高频时钟同步，提供一个负载实例控制信号，一个锁存器在对应于脉冲宽度的数据同时对应于所述波形旋转器的时钟被施加时提供一个时钟，一个计数器按照从锁存器提供的数据确定的起始值对时钟进行计数具有施加的时钟并根据加载实例控制信号加载，并且计数器禁止部分停止计数，直到下一个加载信号在进位结束时进入。

8. 发明授权

US08324060B2 NAND flash memory array having pillar structure and fabricating method of the same 有权
标题翻译：具有柱结构的NAND闪存阵列及其制造方法
公开(公告)号：US08324060B2
公开(公告)日：2012-12-04
申请号：US13222246
申请日：2011-08-31
申请人： Byung Gook Park , Seong Jae Cho
发明人： Byung Gook Park , Seong Jae Cho
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A method is provided for fabricating a NAND flash memory array having vertical channels and sidewall gate structure and a fabricating method of the same. The NAND flash memory array has insulator strip structure and one or more semiconductor strips are next to the both sides of the insulator strip. The NAND flash memory array allows for an improvement of the integrity by decreasing the memory cell area by half and less, and solves the problems of the conventional three-dimensional structure regarding isolation between not only channels but also source/drain regions at the bottom of trenches. The method for fabricating the NAND flash memory array having a pillar structure uses the conventional CMOS process and an etching process with minimum masks, enables to cut down costs.
摘要翻译：提供了一种用于制造具有垂直沟道和侧壁栅极结构的NAND快闪存储器阵列的方法及其制造方法。 NAND闪存阵列具有绝缘体带结构，并且一个或多个半导体条紧邻绝缘体条的两侧。 NAND闪存阵列允许通过将存储器单元面积减小一半或更少来提高整体性，并且解决了传统的三维结构关于不仅仅是通道之间的隔离的问题，而且解决了底部的源极/漏极区域沟渠制造具有柱状结构的NAND快闪存储器阵列的方法使用传统的CMOS工艺和具有最小掩模的蚀刻工艺，能够降低成本。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式