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1. 发明授权

US6043534A High voltage semiconductor device 失效
标题翻译：高压半导体器件
公开(公告)号：US6043534A
公开(公告)日：2000-03-28
申请号：US52142
申请日：1998-03-31
申请人： Seiji Sogo
发明人： Seiji Sogo
IPC分类号： H01L29/78 , H01L21/8249 , H01L27/06 , H01L27/08 , H01L27/092 , H01L29/06 , H01L29/76 , H01L23/58 , H01L29/00 , H01L29/94
CPC分类号： H01L29/0615 , H01L27/0922 , H01L29/0692 , H01L29/0696 , H01L29/7835 , H01L2924/0002
摘要： An N.sup.- - region is formed by diffusion on a P- semiconductor substrate, and a P- region is formed in a surface portion of the N.sup.- - region. A P.sup.+ - region is formed in an outer peripheral portion of the N.sup.- - region, to suppress expansion of a depletion layer of the P- semiconductor substrate when a high voltage is applied. A gate oxide film is formed on the semiconductor substrate, and a gate electrode of polycrystalline silicon is formed on the gate oxide film, particularly on a channel region which is formed by the semiconductor substrate and the P.sup.+ - region, which is as a whole the same as a structure of a lateral N-channel MOSFET. Circuit elements are formed within the N.sup.- - region, and a high voltage is applied. Circuit portions are isolated as the gate electrode and a source region are grounded. This reduces the number of steps for manufacturing a high-insulation IC, increases a breakdown voltage, and integrates the circuit denser.
摘要翻译：通过在P-半导体衬底上的扩散形成N-区，并且在N-区的表面部分中形成P-区。在N-区域的外周部形成有P +区，以在施加高电压时抑制P-半导体衬底的耗尽层的膨胀。在半导体衬底上形成栅极氧化膜，在栅极氧化膜上形成多晶硅栅电极，特别是在由半导体衬底和P +区形成的沟道区上形成，该区域整体上是与横向N沟道MOSFET的结构相同。电路元件形成在N-区内，施加高电压。电路部分被隔离为栅电极，源极区域接地。这减少了用于制造高绝缘IC的步骤数量，增加了击穿电压，并且使电路更密集。

2. 发明授权

US06534829B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06534829B2
公开(公告)日：2003-03-18
申请号：US09321709
申请日：1999-05-28
申请人： Seiji Sogo , Yuji Ueno , Seiki Yamaguchi , Yoshihiro Mori , Yoshiaki Hachiya , Satoru Takahashi , Yuji Yamanishi , Ryuma Hirano
发明人： Seiji Sogo , Yuji Ueno , Seiki Yamaguchi , Yoshihiro Mori , Yoshiaki Hachiya , Satoru Takahashi , Yuji Yamanishi , Ryuma Hirano
IPC分类号： H01L2701
CPC分类号： H01L29/0847 , H01L29/0634 , H01L29/0638 , H01L29/0692 , H01L29/1045 , H01L29/105 , H01L29/66659 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device of the present invention includes: a semiconductor layer of a first conductivity type; source and drain regions of a second conductivity type, which are formed within the semiconductor layer; a channel region provided between the source and drain regions; and a gate electrode formed over the channel region. The device further includes: a buried region of the first conductivity type, at least part of the buried region being included in the drain region; and a heavily doped region of the second conductivity type. The heavily doped region is provided at least between a surface of the semiconductor layer and the buried region. The concentration of a dopant of the second conductivity type in the heavily doped region is higher than that of the dopant of the second conductivity type in the drain region.
摘要翻译：本发明的半导体器件包括：第一导电类型的半导体层; 在半导体层内形成的第二导电类型的源区和漏区; 设置在源区和漏区之间的沟道区; 以及形成在沟道区上的栅电极。所述器件还包括：第一导电类型的掩埋区域，所述掩埋区域的至少一部分包括在所述漏极区域中; 和第二导电类型的重掺杂区域。至少在半导体层的表面和掩埋区域之间设置重掺杂区域。在重掺杂区域中第二导电类型的掺杂剂的浓度高于漏区中第二导电类型的掺杂剂的浓度。

3. 发明授权

US06312996B1 Semiconductor device and method for fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06312996B1
公开(公告)日：2001-11-06
申请号：US09420455
申请日：1999-10-18
申请人： Seiji Sogo
发明人： Seiji Sogo
IPC分类号： H01L21336
CPC分类号： H01L29/0847 , H01L29/0634 , H01L29/66659 , H01L29/7835
摘要： There is provided a method for fabricating a semiconductor device comprising a semiconductor layer of a first conductivity type, a source region of a second conductivity type formed within the semiconductor layer, a drain region of the second conductivity type formed within the semiconductor layer, a channel region provided between the source and drain regions, a gate electrode formed over the channel region, and a buried region of the first conductivity type having at least a part included in the drain region. The method for fabricating the semiconductor device comprises the steps of doping the semiconductor layer with a dopant of the second conductivity type for the drain region and doping the semiconductor layer with a dopant of the first conductivity type for the buried region. The step of doping the semiconductor layer with the dopant of the first conductivity type includes the steps of forming, on the semiconductor layer, a multilayer resist mask having an opening configured to correspond to the buried region and implanting dopant ions of the first conductivity type into the semiconductor layer via the multilayer resist mask by high-energy ion implantation.
摘要翻译：提供一种制造半导体器件的方法，该半导体器件包括第一导电类型的半导体层，形成在半导体层内的第二导电类型的源极区，形成在半导体层内的第二导电类型的漏极区，沟道设置在源区和漏区之间的区域，形成在沟道区上的栅极，以及具有包括在漏区中的至少一部分的第一导电类型的掩埋区。用于制造半导体器件的方法包括以下步骤：用用于漏极区域的第二导电类型的掺杂剂掺杂半导体层，并用掩埋区域的第一导电类型的掺杂剂掺杂半导体层。用第一导电类型的掺杂剂掺杂半导体层的步骤包括以下步骤：在半导体层上形成多层抗蚀剂掩模，该多层抗蚀剂掩模具有构造成对应于掩埋区域的开口并将第一导电类型的掺杂剂离子注入通过高能离子注入通过多层抗蚀剂掩模的半导体层。

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