专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07132854B1 Data path configurable for multiple clocking arrangements 有权
标题翻译：数据通道可配置为多种时钟配置
公开(公告)号：US07132854B1
公开(公告)日：2006-11-07
申请号：US10949537
申请日：2004-09-23
申请人： Suwei Chen , Sanjay Sancheti , Jeffery Scott Hunt
发明人： Suwei Chen , Sanjay Sancheti , Jeffery Scott Hunt
IPC分类号： H03K19/173 , H03K3/289
CPC分类号： G11C7/1045 , G11C7/1006 , G11C7/1012 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1072 , H03K19/1737
摘要： A data path (200) can be configured to accommodate different clocking arrangements. In one mode, data values may be output at a single data rate: one data value every clock cycle. In another mode, data values may be output at a double data rate: two data values every clock cycle. A data path (200) can be compact circuit structure, needing only an additional mode multiplexer (206) and inverter over a conventional D-type master-slave flip-flop.
摘要翻译：数据路径（200）可被配置为适应不同的时钟配置。在一种模式中，数据值可以以单个数据速率输出：每个时钟周期一个数据值。在另一种模式下，数据值可以以双倍数据速率输出：每个时钟周期两个数据值。数据路径（200）可以是紧凑的电路结构，仅需要通过常规D型主从触发器的附加模式多路复用器（206）和反相器。

2. 发明授权

US07135899B1 System and method for reducing skew in complementary signals that can be used to synchronously clock a double data rate output 有权
标题翻译：用于减少互补信号偏移的系统和方法，可用于同步时钟双数据速率输出
公开(公告)号：US07135899B1
公开(公告)日：2006-11-14
申请号：US10844719
申请日：2004-05-13
申请人： Sanjay Sancheti , Suwei Chen
发明人： Sanjay Sancheti , Suwei Chen
IPC分类号： H03L7/00
CPC分类号： H04J3/047 , G06F1/10 , H03K5/151 , H04J3/0685
摘要： A circuit, system, and method are provided for generating edge-aligned, complementary output signals from complementary input signals. The output and input signals can, according to one example, be clock signals. The circuit, system, and method can use the rising edges of the complementary pair of input signals to trigger transitions on the complementary pair of output signals. More specifically, the rising edge of a true input clock signal will trigger the rising edge of the true output clock signal and the falling edge of the inverted output clock signal. A rising edge of the inverted input clock signal will trigger the falling edge of the true output clock signal, and the rising edge of the inverted output clock signal. Moreover, the circuit, system, and method ensures that at any time only one transition occurs on the active inputs of a final logic stage of the clock generation circuit. Also, the circuit, system, and method support double data rate (DDR) data and echo clock generation, where the echo clock transitions in sync with the DDR output.
摘要翻译：提供电路，系统和方法用于从互补输入信号产生边缘对齐的互补输出信号。根据一个示例，输出和输入信号可以是时钟信号。电路，系统和方法可以使用互补输入信号对的上升沿触发互补输出信号对上的转换。更具体地，真实输入时钟信号的上升沿将触发真实输出时钟信号的上升沿和反相输出时钟信号的下降沿。反相输入时钟信号的上升沿将触发真实输出时钟信号的下降沿以及反相输出时钟信号的上升沿。此外，电路，系统和方法确保在时钟发生电路的最终逻辑级的有效输入端上随时只有一个转换。此外，电路，系统和方法支持双数据速率（DDR）数据和回波时钟生成，其中回波时钟与DDR输出同步转换。

3. 发明授权

US07383370B1 Arbiter circuit and signal arbitration method 有权
标题翻译：仲裁电路和信号仲裁方法
公开(公告)号：US07383370B1
公开(公告)日：2008-06-03
申请号：US11384748
申请日：2006-03-20
申请人： Sanjay Sancheti , Gareth Feighery
发明人： Sanjay Sancheti , Gareth Feighery
IPC分类号： G06F13/00
CPC分类号： G06F13/14 , G06F13/1605
摘要： An arbiter circuit (100) can include a latch circuit (102) that latches competing input signals (MATCH1 and MATCH2) to generate signals on latch output (110-0 and 110-1). A filter section (104) can prevent metastable states of latch output signals from propagating through to output signals (BUSY2 and BUSY1). In addition, filter section (104) can generate output signals (BUSY2 and BUSY1) having one set of values when both inputs are inactive, and a second set of values when latch (102) is in the metastable state.
摘要翻译：仲裁器电路（100）可以包括锁存电路（102），其锁存竞争输入信号（MATCH 1和MATCH 2）以在锁存器输出（110 - 0和110 - 1）上产生信号。滤波器部分（104）可以防止锁存器输出信号的亚稳态传播到输出信号（BUSY 2和BUSY 1）。此外，当两个输入不活动时，滤波器部分（104）可以产生具有一组值的输出信号（BUSY 2和BUSY 1），以及当锁存器（102）处于亚稳态时的第二组值。

4. 发明授权

US07113445B1 Multi-port memory cell and access method 有权
标题翻译：多端口存储单元和访问方式
公开(公告)号：US07113445B1
公开(公告)日：2006-09-26
申请号：US10948006
申请日：2004-09-22
申请人： Sanjay Sancheti , Jeffery Scott Hunt , George M. Ansel
发明人： Sanjay Sancheti , Jeffery Scott Hunt , George M. Ansel
IPC分类号： G11C8/00
CPC分类号： G11C11/412
摘要： A multi-port memory cell (200) can be formed from seven transistors. Single ended write operations can be performed without a boosted word line voltage or variable power supply. A data value (D/DB) stored in the memory cell (200) can be cleared by shorting complementary data nodes (204-0 and 204-1) together. Write data can then be placed on a bit line. Complementary data nodes (204-0 and 204-1) can then be isolated once again, resulting in the write data being latched within the memory cell (300). An access method (700) for a multi-port memory cell is also described.
摘要翻译：多端口存储单元（200）可以由七个晶体管形成。可以在没有增强字线电压或可变电源的情况下执行单端写操作。存储在存储单元（200）中的数据值（D / DB）可以通过将互补数据节点（204-0和204-1）一起短路来清除。然后可以将数据写入位线。然后可以再次分离互补数据节点（204-0和204-1），导致写数据被锁存在存储单元（300）内。还描述了用于多端口存储器单元的访问方法（700）。

5. 发明授权

US06710636B1 Method and system for high resolution delay lock loop 失效
标题翻译：高分辨率延迟锁定环的方法和系统
公开(公告)号：US06710636B1
公开(公告)日：2004-03-23
申请号：US10264692
申请日：2002-10-03
申请人： Gary Gibbs , Lingsong Xu , Sanjay Sancheti
发明人： Gary Gibbs , Lingsong Xu , Sanjay Sancheti
IPC分类号： H03L706
CPC分类号： H03L7/10 , H03L7/0814 , H03L7/0818
摘要： A method for utilizing a delay lock loop to cover a wide delay range. In one method embodiment, the present invention receives a reference clock pulse. Next, in a first loop, a phase variation is adjusted between the feedback clock pulse and the reference clock pulse utilizing a coarse delay in conjunction with a first fine delay. The resulting pulse is then output to a chip delay and then sent back to the delay lock loop as a feedback clock pulse. Additionally, in a second loop, the phase variation is adjusted between said second loop and said first loop utilizing the coarse delay in conjunction with a second fine delay, wherein the second fine delay has a delay range for adjusting the phase variation which overlaps the delay range of the first fine delay of the first loop.
摘要翻译：一种利用延迟锁定环来覆盖宽延迟范围的方法。在一个方法实施例中，本发明接收参考时钟脉冲。接下来，在第一循环中，利用与第一精细延迟相结合的粗略延迟，在反馈时钟脉冲和参考时钟脉冲之间调整相位变化。然后将产生的脉冲输出到芯片延迟，然后作为反馈时钟脉冲发送回延迟锁定环。另外，在第二环路中，利用与第二精细延迟相结合的粗略延迟，在所述第二环路和所述第一环路之间调整相位变化，其中第二精细延迟具有用于调整与延迟重叠的相位变化的延迟范围第一个循环的第一个精细延迟的范围。

6. 发明授权

US6100739A Self-timed synchronous pulse generator with test mode 有权
标题翻译：具有测试模式的自定时同步脉冲发生器
公开(公告)号：US6100739A
公开(公告)日：2000-08-08
申请号：US150551
申请日：1998-09-09
申请人： George M. Ansel , Sanjay Sancheti
发明人： George M. Ansel , Sanjay Sancheti
IPC分类号： G11C7/10 , G11C29/02 , H03K5/135 , H03K3/037
CPC分类号： G11C29/02 , G11C7/1072 , H03K5/135
摘要： A circuit and method comprising (a) a first circuit configured to generate an output signal having a variable pulse width in response to an (i) input signal and (ii) a control signal and (b) a second circuit configured to generate the control signal in response to (i) the input signal and (ii) a test input. In one example, the first circuit may comprise a register configured to present the output signal and an edge detection circuit configured to present a second control signal to said second circuit. In another example, the second circuit may comprise a plurality of first gates that may generate the output signal in further response to the second control signal.
摘要翻译：一种电路和方法，包括：（a）第一电路，被配置为响应于（i）输入信号和（ii）控制信号产生具有可变脉冲宽度的输出信号，以及（b）被配置为产生控制的第二电路响应于（i）输入信号和（ii）测试输入的信号。在一个示例中，第一电路可以包括配置为呈现输出信号的寄存器和被配置为向第二电路呈现第二控制信号的边沿检测电路。在另一示例中，第二电路可以包括可以进一步响应于第二控制信号而产生输出信号的多个第一门。

7. 发明授权

US5963487A Write enabling circuitry for a semiconductor memory 失效
标题翻译：写半导体存储器的使能电路
公开(公告)号：US5963487A
公开(公告)日：1999-10-05
申请号：US991231
申请日：1997-12-16
申请人： Shiva P. Gowni , Sudhir S. Moharir , Sanjay Sancheti
发明人： Shiva P. Gowni , Sudhir S. Moharir , Sanjay Sancheti
IPC分类号： G11C7/10 , G11C7/22 , G11C7/00
CPC分类号： G11C7/1045 , G11C7/1078 , G11C7/22
摘要： A write control circuit for a semiconductor memory device includes a conventional write path responsive to a control input (e.g., an external write enable signal) to control the beginning of a write operation for a write driver, whilst a separate dedicated write disable path, responsive to the same control input, controls the end of the write operation for the write driver. The invention separates the end of write from the beginning of write by introducing a fast dedicated path designed primarily for ending the write. This dedicated path contains dedicated logic to generate an end of write signal at the disabling edge of the control input to disable the write driver quickly before a new memory cell is selected.
摘要翻译：用于半导体存储器件的写入控制电路包括响应于控制输入（例如，外部写入使能信号）的常规写入路径，以控制写入驱动器的写入操作的开始，同时单独的专用写入禁止路径到相同的控制输入，控制写入驱动器的写入操作的结束。本发明通过引入主要用于结束写入的快速专用路径将写入结束与写入开始分开。该专用路径包含专用逻辑，用于在控制输入的禁止边缘产生写入信号的结束，以在选择新的存储器单元之前快速禁用写入驱动器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式