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1. 发明授权

US09652611B2 Mitigating a compromised network on chip 有权
公开(公告)号：US09652611B2
公开(公告)日：2017-05-16
申请号：US14712777
申请日：2015-05-14
申请人： Dean Michael Ancajas , Koushik Chakraborty , Sanghamitra Roy
发明人： Dean Michael Ancajas , Koushik Chakraborty , Sanghamitra Roy
IPC分类号： H04L29/06 , H04L9/00 , G06F21/55 , G06F21/56 , G06F21/85
CPC分类号： G06F21/55 , G06F21/56 , G06F21/85
摘要： For mitigating a compromised network-on-chip, code appends a node identifier of a destination node to a packet transmitted in a multiprocessor system-on-chip (MPSOC). The MPSOC may include third-party components such as a network-on-chip. The code may detect a copy of the packet from the node identifier. In addition, the code may drop the copy of the packet in response to the copy of the packet being routed to an unintended node.

2. 发明申请

US20110185328A1 System and Method for Circuit Design Floorplanning 有权
标题翻译：电路设计布局规划的系统与方法
公开(公告)号：US20110185328A1
公开(公告)日：2011-07-28
申请号：US13013654
申请日：2011-01-25
申请人： Sanghamitra Roy , Koushik Chakraborty , Yiding Han
发明人： Sanghamitra Roy , Koushik Chakraborty , Yiding Han
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Circuit floorplanning is performed on a combination central processing unit and multiprocessor. A B*-tree data structure of a floorplan and circuit related constants reside in a central processing unit data storage. The B* tree structure of a floorplan along and said circuit related constants are copied to a multiprocessor data storage where multiple thread blocks, each consisting of a single thread, copy the tree to their own shared memories. The multiprocessor concurrently evaluates different moves in different thread blocks. The multiprocessor then evaluates objective function results and stores those results. The best result for floorplanning is selected from the multiple circuit evaluations.
摘要翻译：电路布局规划在组合中央处理单元和多处理器上执行。平面图和电路相关常数的B *树数据结构驻留在中央处理单元数据存储器中。平面布局图的B *树结构和所述电路相关常数被复制到多处理器数据存储器，其中多个线程块（每个由单个线程组成）将树复制到它们自己的共享存储器。多处理器同时评估不同线程块中的不同移动。然后，多处理器评估目标函数结果并存储这些结果。从多电路评估中选择布局规划的最佳结果。

3. 发明申请

US20160285899A1 RUNTIME DETECTION OF A BANDWIDTH DENIAL ATTACK FROM A ROGUE INTERCONNECT 审中-公开
标题翻译：从一个ROGUE INTERCONNECT进行的带宽干扰攻击的运行时间检测
公开(公告)号：US20160285899A1
公开(公告)日：2016-09-29
申请号：US15079486
申请日：2016-03-24
申请人： Rajesh Jayashankara Shridevi , Dean Michael Ancajas , Koushik Chakraborty , Sanghamitra Roy
发明人： Rajesh Jayashankara Shridevi , Dean Michael Ancajas , Koushik Chakraborty , Sanghamitra Roy
IPC分类号： H04L29/06 , H04L12/933
CPC分类号： H04L63/1416 , H04L49/109 , H04L63/1458
摘要： For runtime detection of a bandwidth denial attack from a rogue NoC. The apparatus includes a processor and a memory storing code executable by the processor. The processor generates a plurality of proximal analogous packets each corresponding to a given packet traversing a multiprocessor system-on-chips (MPSoC). Each proximal analogous packet includes one or more of a proximal source modified from a given packet source and a proximal destination modified from a given packet destination. The processor further compares traversal latencies between each proximal analogous packet/given packet pair. In addition, the processor detects a rogue interconnect in response to aggregate variations in the traversal latencies.
摘要翻译：对于来自流氓NoC的带宽拒绝攻击的运行时间检测。该装置包括处理器和存储可由处理器执行的代码的存储器。处理器产生多个近似类似的数据包，每个对应于穿过多处理器片上系统（MPSoC）的给定数据包。每个近似类型分组包括从给定分组源修改的近端源和从给定分组目的地修改的近端目的地的一个或多个。处理器进一步比较每个近似类似分组/给定分组对之间的遍历延迟。此外，处理器响应于遍历延迟中的聚合变化来检测流氓互连。

4. 发明授权

US10057281B2 Runtime detection of a bandwidth denial attack from a rogue interconnect 有权
公开(公告)号：US10057281B2
公开(公告)日：2018-08-21
申请号：US15079486
申请日：2016-03-24
申请人： Rajesh Jayashankara Shridevi , Dean Michael Ancajas , Koushik Chakraborty , Sanghamitra Roy
发明人： Rajesh Jayashankara Shridevi , Dean Michael Ancajas , Koushik Chakraborty , Sanghamitra Roy
IPC分类号： G06F11/00 , H04L29/06 , H04L12/933
CPC分类号： H04L63/1416 , H04L49/109 , H04L63/1458
摘要： For runtime detection of a bandwidth denial attack from a rogue NoC. The apparatus includes a processor and a memory storing code executable by the processor. The processor generates a plurality of proximal analogous packets each corresponding to a given packet traversing a multiprocessor system-on-chips (MPSoC). Each proximal analogous packet includes one or more of a proximal source modified from a given packet source and a proximal destination modified from a given packet destination. The processor further compares traversal latencies between each proximal analogous packet/given packet pair. In addition, the processor detects a rogue interconnect in response to aggregate variations in the traversal latencies.

5. 发明授权

US09063667B2 Dynamic memory relocation 有权
标题翻译：动态内存重定位
公开(公告)号：US09063667B2
公开(公告)日：2015-06-23
申请号：US14056690
申请日：2013-10-17
申请人： Dean Michael Ancajas , Koushik Chakraborty , Sanghamitra Roy
发明人： Dean Michael Ancajas , Koushik Chakraborty , Sanghamitra Roy
IPC分类号： G06F12/00 , G06F3/06 , G06F13/00
CPC分类号： G06F3/0647 , G06F3/0604 , G06F3/0605 , G06F3/0638 , G06F3/0683 , G06F3/0688
摘要： For dynamic memory relocation, a tracking module tracks accesses to a plurality of memory devices. Each of the plurality of memory devices is in communication with one memory controller of a plurality of memory controllers embedded in a computing device comprising a plurality of nodes. A migration module migrates first data from a first memory device in communication with a first memory controller to a second memory device in communication with a second memory controller.
摘要翻译：对于动态存储器重定位，跟踪模块跟踪对多个存储器件的访问。多个存储器设备中的每一个与嵌入在包括多个节点的计算设备中的多个存储器控制器的一个存储器控制器通信。迁移模块将来自与第一存储器控制器通信的第一存储器设备的第一数据迁移到与第二存储器控制器通信的第二存储器设备。

6. 发明申请

US20150100930A1 Sustainable Differentially Reliable Architecture for Dark Silicon 有权
标题翻译：可持续的差异性可靠的黑硅结构
公开(公告)号：US20150100930A1
公开(公告)日：2015-04-09
申请号：US14046335
申请日：2013-10-04
申请人： Jason M. Allred , Koushik Chakraborty , Sanghamitra Roy
发明人： Jason M. Allred , Koushik Chakraborty , Sanghamitra Roy
IPC分类号： G06F17/50
CPC分类号： G06F9/5044 , G06F11/2028 , G06F2209/5018 , Y02D10/22
摘要： For mapping a sustainable, differentially reliable architecture for dark silicon, a calculation module calculates an expected energy efficiency for a prior mapping of process threads for a plurality of cores. The calculation module further calculates a workload acceptance capacity (WAC) from degradation rates for the plurality of cores. A map module maps the process threads to the plurality of cores based on at least one of the expected energy efficiency and the WAC to satisfy a mapping policy. A specified number of the plurality of cores is not powered.
摘要翻译：为了绘制用于暗硅的可持续的，差异可靠的架构，计算模块计算用于多个核的过程线程的先前映射的预期能量效率。计算模块进一步从多个核的劣化率计算工作负载接受容量（WAC）。地图模块基于预期能量效率和WAC中的至少一个来将进程线程映射到多个核心以满足映射策略。指定数量的多个核心未被供电。

7. 发明申请

US20150095872A1 GLOBAL ROUTER USING GRAPHICS PROCESSING UNIT 有权
标题翻译：使用图形处理单元的全局路由器
公开(公告)号：US20150095872A1
公开(公告)日：2015-04-02
申请号：US14505374
申请日：2014-10-02
申请人： Yiding Han , Koushik Chakraborty , Sanghamitra Roy
发明人： Yiding Han , Koushik Chakraborty , Sanghamitra Roy
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： For global routing using a graphics processing unit (GPU), a method routes a net of node interconnections for a semiconductor design. In addition, the method decomposes the net into subnets. Each subnet has no shared paths. The method further identifies a congested region of the routed net that exceeds routing capacities. In addition, the method correlates the congested region with a plurality of first subnets with workloads within the congested region. The method routes the subnets in parallel using the GPU.
摘要翻译：对于使用图形处理单元（GPU）的全局路由，一种方法将半导体设计的节点互连网络进行路由。此外，该方法将网络分解为子网。每个子网都没有共享路径。该方法还识别出路由网络的拥塞区域超过路由能力。另外，该方法使拥塞区域与多个第一子网与拥塞区域内的工作负载相关。该方法使用GPU并行地对子网进行路由。

8. 发明申请

US20150049758A1 HOT CARRIER INJECTION TOLERANT NETWORK ON CHIP ROUTER ARCHITECTURE 审中-公开
标题翻译：热载体注射耐火网络在芯片路由器架构上
公开(公告)号：US20150049758A1
公开(公告)日：2015-02-19
申请号：US14056804
申请日：2013-10-17
申请人： Dean Michael Ancajas , Koushik Chakraborty , Sanghamitra Roy
发明人： Dean Michael Ancajas , Koushik Chakraborty , Sanghamitra Roy
IPC分类号： H04L12/931
CPC分类号： H04L49/15 , H04L49/109
摘要： For a hot carrier injection tolerant network on chip (NoC) router architecture, a coupling module modifies couplings of connecting wires to input buffer data bits in an NoC data channel. A connection module modifies connection points of an input buffer to the connecting wires.
摘要翻译：对于热载流子注入容忍的片上网络（NoC）路由器架构，耦合模块将连接线的耦合修改为NoC数据通道中的输入缓冲器数据位。连接模块将输入缓冲器的连接点修改为连接线。

9. 发明授权

US08549456B2 System and method for circuit design floorplanning 有权
标题翻译：电路设计布局规划的系统和方法
公开(公告)号：US08549456B2
公开(公告)日：2013-10-01
申请号：US13013654
申请日：2011-01-25
申请人： Sanghamitra Roy , Koushik Chakraborty , Yiding Han
发明人： Sanghamitra Roy , Koushik Chakraborty , Yiding Han
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Circuit floorplanning is performed on a combination central processing unit and multiprocessor. A B*-tree data structure of a floorplan and circuit related constants reside in a central processing unit data storage. The B* tree structure of a floorplan along and said circuit related constants are copied to a multiprocessor data storage where multiple thread blocks, each consisting of a single thread, copy the tree to their own shared memories. The multiprocessor concurrently evaluates different moves in different thread blocks. The multiprocessor then evaluates objective function results and stores those results. The best result for floorplanning is selected from the multiple circuit evaluations.
摘要翻译：电路布局规划在组合中央处理单元和多处理器上执行。平面图和电路相关常数的B *树数据结构驻留在中央处理单元数据存储器中。平面布局图的B *树结构和所述电路相关常数被复制到多处理器数据存储器，其中多个线程块（每个由单个线程组成）将树复制到它们自己的共享存储器。多处理器同时评估不同线程块中的不同移动。然后，多处理器评估目标函数结果并存储这些结果。从多电路评估中选择布局规划的最佳结果。

10. 发明授权

US09396302B2 Global router using graphics processing unit 有权
标题翻译：全局路由器使用图形处理单元
公开(公告)号：US09396302B2
公开(公告)日：2016-07-19
申请号：US14505374
申请日：2014-10-02
申请人： Yiding Han , Koushik Chakraborty , Sanghamitra Roy
发明人： Yiding Han , Koushik Chakraborty , Sanghamitra Roy
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： For global routing using a graphics processing unit (GPU), a method routes a net of node interconnections for a semiconductor design. In addition, the method decomposes the net into subnets. Each subnet has no shared paths. The method further identifies a congested region of the routed net that exceeds routing capacities. In addition, the method correlates the congested region with a plurality of first subnets with workloads within the congested region. The method routes the subnets in parallel using the GPU.
摘要翻译：对于使用图形处理单元（GPU）的全局路由，一种方法将半导体设计的节点互连网络进行路由。此外，该方法将网络分解为子网。每个子网都没有共享路径。该方法还识别出路由网络的拥塞区域超过路由能力。另外，该方法使拥塞区域与多个第一子网与拥塞区域内的工作负载相关。该方法使用GPU对并行的子网进行路由。

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