专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US4864372A Field effect transistor 失效
标题翻译：场效应晶体管
公开(公告)号：US4864372A
公开(公告)日：1989-09-05
申请号：US835707
申请日：1986-03-03
申请人： Sanehiko Kakihana
发明人： Sanehiko Kakihana
IPC分类号： H01L21/265 , H01L21/266 , H01L21/338 , H01L29/10
CPC分类号： H01L29/66871 , H01L21/26586 , H01L21/266 , H01L29/1029
摘要： This disclosure depicts a novel semiconductor device and the method of making it. A novel field effect transistor (FET) has a channel region which is heavily doped under the gate and between the gate and the source of the FET. The channel region between the gate and the drain is lightly doped. The FET is formed on a heavily doped semiconductor substrate. The method of making the novel FET comprises providing a mask layer over a lightly doped channel region and forming openings in the mask layer such that a portion of the mask is located at the gate location and has a predetermined width and height.
摘要翻译：本公开描述了一种新颖的半导体器件及其制造方法。一种新颖的场效应晶体管（FET）具有在栅极之下以及FET的栅极和源极之间重掺杂的沟道区。栅极和漏极之间的沟道区域被轻掺杂。 FET在重掺杂的半导体衬底上形成。制造新型FET的方法包括在轻掺杂沟道区上提供掩模层，并在掩模层中形成开口，使得掩模的一部分位于栅极位置并具有预定的宽度和高度。

2. 发明授权

US4826070A Die attachment process 失效
标题翻译：模具附着工艺
公开(公告)号：US4826070A
公开(公告)日：1989-05-02
申请号：US104882
申请日：1987-10-05
申请人： Sanehiko Kakihana
发明人： Sanehiko Kakihana
IPC分类号： H01L21/52 , H01L21/00 , B23K31/00
CPC分类号： H01L24/32 , H01L21/67121 , H01L2224/29111 , H01L2224/29144 , H01L2224/32225 , H01L2924/01006 , H01L2924/01015 , H01L2924/01033 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/0132 , H01L2924/10158 , H01L2924/10329 , H01L2924/1306 , H01L2924/14
摘要： Disclosed is a process for attaching a die to a package, which process utilizes a heat cycle in conjunction with a vacuum in the attachment process.
摘要翻译：公开了一种将模具附接到包装的方法，该方法利用在连接过程中结合真空的热循环。

3. 发明授权

US4792531A Self-aligned gate process 失效
标题翻译：自对准门过程
公开(公告)号：US4792531A
公开(公告)日：1988-12-20
申请号：US105650
申请日：1987-10-05
申请人： Sanehiko Kakihana
发明人： Sanehiko Kakihana
IPC分类号： H01L29/812 , H01L21/285 , H01L21/338 , H01L21/265 , H01L21/44 , H01L21/48
CPC分类号： H01L29/66871 , H01L21/28587 , Y10S148/14
摘要： Disclosed is a process for producing a field effect transistor to provide a uniformity of spacing between the gate and drain as well as the gate and source.
摘要翻译：公开了一种用于产生场效应晶体管以提供栅极和漏极以及栅极和源极之间的间隔的均匀性的方法。

4. 发明授权

US5225369A Tunnel diode detector for microwave frequency applications 失效
标题翻译：隧道二极管检测器用于微波频率应用
公开(公告)号：US5225369A
公开(公告)日：1993-07-06
申请号：US787300
申请日：1991-11-04
申请人： Chung-Yi Su , Sanehiko Kakihana , Domingo A. Figueredo
发明人： Chung-Yi Su , Sanehiko Kakihana , Domingo A. Figueredo
IPC分类号： H01L29/88
CPC分类号： H01L29/88 , Y10S438/979
摘要： A tunnel diode is disclosed having a highly P-doped layer of indium gallium arsenide formed on a highly N-doped layer of indium gallium arsenide which is supported on a semi-insulating substrate of indium phosphide. In an alternative embodiment, a tunnel diode is disclosed which has a highly P-doped layer of indium gallium arsenide formed on a highly N-doped layer of indium gallium arsenide which is supported on an N-doped substrate.
摘要翻译：公开了一种隧道二极管，其具有形成在铟镓砷的高N掺杂层上的高P掺杂的砷化铟镓层，其被支撑在磷化铟的半绝缘衬底上。在替代实施例中，公开了一种隧道二极管，其具有形成在支撑在N掺杂衬底上的铟镓砷化物的高N掺杂层上的高掺杂砷化铟镓层。

5. 发明授权

US4698899A Field effect transistor 失效
标题翻译：场效应晶体管
公开(公告)号：US4698899A
公开(公告)日：1987-10-13
申请号：US835706
申请日：1986-03-03
申请人： Sanehiko Kakihana
发明人： Sanehiko Kakihana
IPC分类号： H01L21/265 , H01L21/338 , H01L29/10 , H01L21/42
CPC分类号： H01L29/66871 , H01L21/26586 , H01L29/1029 , Y10S148/082
摘要： This disclosure depicts a novel semiconductor device and the method of making it. A novel field effect transistor (FET) has a channel region which is heavily doped under the gate and between the gate and the source of the FET. The channel region between the gate and the drain is lightly doped. The FET is formed on a heavily doped semiconductor substrate. The method of making the novel FET comprises providing a mask layer over a lightly doped channel region and forming openings in the mask layer such that a portion of the mask is located at the gate location and has a predetermined width and height. Ion implanting is performed at a predetermined angle such that a first portion of the channel adjacent the source is heavily doped and a second portion of the channel adjacent the drain is not exposed due to the height of the mask at the gate.
摘要翻译：本公开描述了一种新颖的半导体器件及其制造方法。一种新颖的场效应晶体管（FET）具有在栅极之下以及FET的栅极和源极之间重掺杂的沟道区。栅极和漏极之间的沟道区域被轻掺杂。 FET在重掺杂的半导体衬底上形成。制造新型FET的方法包括在轻掺杂沟道区上提供掩模层，并在掩模层中形成开口，使得掩模的一部分位于栅极位置并具有预定的宽度和高度。以预定角度执行离子注入，使得邻近源极的沟道的第一部分被重掺杂，并且与栅极相邻的沟道的第二部分由于掩模在栅极处的高度而不被暴露。

6. 发明授权

US5093692A Tunnel diode detector for microwave frequency applications 失效
标题翻译：隧道二极管检测器用于微波频率应用
公开(公告)号：US5093692A
公开(公告)日：1992-03-03
申请号：US612152
申请日：1990-11-09
申请人： Chung-Yi Su , Sanehiko Kakihana , Domingo A. Figueredo
发明人： Chung-Yi Su , Sanehiko Kakihana , Domingo A. Figueredo
IPC分类号： H01L29/88
CPC分类号： H01L29/88
摘要： A tunnel diode is disclosed having a highly P-doped layer of indium gallium arsenide formed on a highly N-doped layer of indium gallium arsenide which is supported on a semi-insulating substrate of indium phosphide. In an alternative embodiment, a tunnel diode is disclosed which has a highly P-doped layer of indium gallium arsenide formed on a highly N-doped layer of indium gallium arsenide which is supported on an N-doped substrate.
摘要翻译：公开了一种隧道二极管，其具有形成在铟镓砷的高N掺杂层上的高P掺杂的砷化铟镓层，其被支撑在磷化铟的半绝缘衬底上。在替代实施例中，公开了一种隧道二极管，其具有形成在支撑在N掺杂衬底上的铟镓砷化物的高N掺杂层上的高掺杂砷化铟镓层。

7. 发明授权

US5034347A Process for producing an integrated circuit device with substrate via hole and metallized backplane 失效
标题翻译：用于制造具有衬底通孔和金属化背板的集成电路器件的工艺
公开(公告)号：US5034347A
公开(公告)日：1991-07-23
申请号：US575242
申请日：1990-08-30
申请人： Sanehiko Kakihana
发明人： Sanehiko Kakihana
IPC分类号： H01L21/74 , H01L23/48
CPC分类号： H01L21/743 , H01L23/481 , H01L2924/0002 , H01L2924/3011 , Y10S438/945
摘要： Disclosed is a process for producing a monolithic microwave integrated circuit device utilizing a body having a first thickness in the heat producing region and a second thickness in the region adjacent to the microstrip transmission lines.
摘要翻译：公开了一种利用在发热区域中具有第一厚度的主体和在与微带传输线相邻的区域中的第二厚度的单片微波集成电路器件的制造方法。

8. 发明授权

US4906956A On-chip tuning for integrated circuit using heat responsive element 失效
标题翻译：使用热响应元件的集成电路的片上调谐
公开(公告)号：US4906956A
公开(公告)日：1990-03-06
申请号：US105643
申请日：1987-10-05
申请人： Sanehiko Kakihana
发明人： Sanehiko Kakihana
IPC分类号： H01L27/04 , H01L21/822 , H01P3/08 , H01P5/02 , H01P11/00
CPC分类号： H01P11/00
摘要： Disclosed is a tunable circuit for an integrated circuit device and a process for making such circuit.
摘要翻译：公开了用于集成电路器件的可调谐电路和用于制造这种电路的工艺。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式