专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06999106B2 Reducing the bias on silicon light modulators 有权
标题翻译：降低硅光调制器的偏差
公开(公告)号：US06999106B2
公开(公告)日：2006-02-14
申请号：US09846065
申请日：2001-04-30
申请人： Samson X. Huang
发明人： Samson X. Huang
IPC分类号： G09G5/10
CPC分类号： G09G3/36 , G02F1/136277
摘要： A negative bias voltage may be utilized to bias a spatial light modulator and to enable the spatial light modulator to be modulated using relatively low supply voltages. During the negative frame, a positive bias voltage may be utilized and during the positive frame, a negative bias voltage may be utilized. This avoids damage to the liquid crystal material. The necessary modulating voltages may be within the range available from leading edge silicon technologies.
摘要翻译：负偏置电压可以用于偏置空间光调制器并且使得能够使用相对低的电源电压来调制空间光调制器。在负帧期间，可以使用正偏置电压，并且在正帧期间可以利用负偏置电压。这避免了液晶材料的损坏。必要的调制电压可以在领先的硅技术的范围内。

2. 发明授权

US07230600B1 Repairable memory in display devices 有权
标题翻译：显示设备中的可修复内存
公开(公告)号：US07230600B1
公开(公告)日：2007-06-12
申请号：US09675067
申请日：2000-09-28
申请人： Samson X. Huang
发明人： Samson X. Huang
IPC分类号： G09G3/36
CPC分类号： G11C29/846
摘要： A display system includes a repairable memory that re-routes data when a defect exists in the memory. A significant bit in the display memory that would otherwise be corrupted by a bad memory cell is re-routed to a least significant bit position in the memory, and the least significant information is discarded. The repairable memory includes a memory device and two repair routers. One repair router is on the input of the memory, and one repair router is on the output of the memory. One or more least significant bits can be sacrificed to preserve more significant bit information.
摘要翻译：显示系统包括当存储器中存在缺陷时重新路由数据的可修复存储器。否则将被坏的存储器单元破坏的显示存储器中的有效位重新路由到存储器中的最低有效位位置，并且丢弃最不重要的信息。可修复存储器包括存储器设备和两个修复路由器。一个维修路由器位于内存的输入端，一个修复路由器位于内存的输出端。可以牺牲一个或多个最低有效位以保留更重要的位信息。

3. 发明授权

US07136211B2 Display device with non-linear ramp 有权
标题翻译：具有非线性斜坡的显示设备
公开(公告)号：US07136211B2
公开(公告)日：2006-11-14
申请号：US10991846
申请日：2004-11-17
申请人： Samson X. Huang , Thomas E. Willis
发明人： Samson X. Huang , Thomas E. Willis
IPC分类号： G02B26/00 , G02F1/03 , G09G5/00 , G09G5/10 , G09G3/34 , G09G3/36
CPC分类号： G09G3/34 , G09G3/346 , G09G3/3648 , G09G2310/0259 , G09G2310/027 , G09G2310/066 , G09G2320/0276
摘要： In some embodiments, a drive circuit may be coupled to a spatial light modulator, wherein the drive circuit provides a non-linear analog ramp signal to the spatial light modulator. Other embodiments are disclosed and claimed.
摘要翻译：在一些实施例中，驱动电路可以耦合到空间光调制器，其中驱动电路向空间光调制器提供非线性模拟斜坡信号。公开和要求保护其他实施例。

4. 发明授权

US5228002A First-in first-out memory device and method for accessing the device 失效
标题翻译：先进先出的存储设备和访问设备的方法
公开(公告)号：US5228002A
公开(公告)日：1993-07-13
申请号：US691996
申请日：1991-04-26
申请人： Samson X. Huang
发明人： Samson X. Huang
IPC分类号： G06F5/10 , G06F5/14
CPC分类号： G06F5/14
摘要： To reduce the access time of a FIFO, a storage device is provided for storing pre-loaded data to be read from the memory array of the FIFO. Thus during each read operation, the pre-loaded data in the storage device is read and the next unit of data to be read during the next read operation is pre-loaded from the array into the storage device. A second storage device is provided for storing the first unit of data written into the array after the array is empty. Thus during the first read operation after the array is rendered non-empty by one or more consecutive write operations, the first unit of data stored in the second storage device is read during the first read operation. This avoids reading garbage from the first storage device which is pre-loaded during the last read operation before the FIFO is empty.
摘要翻译：为了减少FIFO的访问时间，提供存储设备用于存储要从FIFO的存储器阵列读取的预加载数据。因此，在每次读取操作期间，读取存储设备中的预加载数据，并且将在下一次读取操作期间要读取的下一个要读取的数据单元从阵列预加载到存储设备中。第二存储装置被提供用于在数组为空之后存储写入阵列的第一数据单元。因此，在通过一个或多个连续写入操作使数组变为非空之后的第一读取操作期间，在第一读取操作期间读取存储在第二存储设备中的第一数据单元。这避免了在FIFO为空之前在最后一次读操作期间预加载的第一存储设备的垃圾。

5. 发明授权

US07119779B2 Display device refresh 有权
标题翻译：显示设备刷新
公开(公告)号：US07119779B2
公开(公告)日：2006-10-10
申请号：US10396579
申请日：2003-03-25
申请人： Samson X. Huang
发明人： Samson X. Huang
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G3/20 , G09G3/3648 , G09G2300/0842 , G09G2310/0259 , G09G2330/021
摘要： Some embodiments provide application, at a beginning of a first display frame, of a first potential to a pixel imaging element, the first potential to reset the pixel imaging element to a reset state, application, during the first display frame, of a second potential to the pixel imaging element, the second potential to set the pixel imaging element to a desired imaging state, and change, at a beginning of a second display frame subsequent to the first display frame, of the second potential to a third potential, the third potential to reset the pixel imaging element to the reset state.
摘要翻译：一些实施例在第一显示帧的开始处提供对像素成像元件的第一电位的应用，第一电位将像素成像元件复位到复位状态，在第一显示帧期间应用第二电位将所述像素成像元件设置为期望的成像状态的第二电位，并且将所述第二电位的第二显示帧之后的第二显示帧的开始处改变为第三电位，所述第三电位将像素成像元件复位到复位状态的可能性。

6. 发明授权

US06731272B2 Pseudo static memory cell for digital light modulator 有权
标题翻译：数字光调制器的伪静态存储单元
公开(公告)号：US06731272B2
公开(公告)日：2004-05-04
申请号：US09768028
申请日：2001-01-22
申请人： Samson X. Huang
发明人： Samson X. Huang
IPC分类号： G09G500
CPC分类号： G09G3/3648 , G09G3/2018 , G09G3/3659 , G09G2300/0809 , G09G2300/0828 , G09G2300/0842
摘要： A digital driver formed a liquid crystal uses a pseudo static memory cell formed of two transistors to hold the charge that will be applied to the different parts of the liquid crystal. The pseudo static memory is formed of two transistors, one of which is a pass transistor which passes the digital value and then goes into a high impedance date. The other transistor is a transistor configured to use its gate capacitance to store the charge. When the charge is above a specified level, it acts like a digital one and turns on the transistor. Conversely, when the charge is below level, it acts like a digital zero, turning off the transistor.
摘要翻译：形成液晶的数字驱动器使用由两个晶体管形成的伪静态存储单元来保持将被施加到液晶的不同部分的电荷。伪静态存储器由两个晶体管组成，其中之一是传递数字值然后进入高阻抗日期的传输晶体管。另一个晶体管是被配置为使用其栅极电容来存储电荷的晶体管。当电荷高于指定电平时，它的作用就像数字电平，并打开晶体管。相反，当电荷低于电平时，它的作用就像数字零，关闭晶体管。

7. 发明授权

US6021500A Processor with sleep and deep sleep modes 失效
标题翻译：具有睡眠和深度睡眠模式的处理器
公开(公告)号：US6021500A
公开(公告)日：2000-02-01
申请号：US852174
申请日：1997-05-07
申请人： Tsan-Kuen Wang , Samson X. Huang , Mustafiz R. Choudhury , Edward T. Grochowski
发明人： Tsan-Kuen Wang , Samson X. Huang , Mustafiz R. Choudhury , Edward T. Grochowski
IPC分类号： G06F1/32
CPC分类号： G06F1/3203
摘要： A processor has a clock generator circuit, a sleep pin that receives an external sleep signal, and a first interface circuit coupled to the clock generator circuit and the sleep pin. The clock generator circuit generates a core clock signal and a bus clock signal in response to an external clock signal. When the external sleep signal is asserted, the processor enters a sleep state when the core clock signal and the bus clock signal are in a first predetermined relationship with each other.
摘要翻译：处理器具有时钟发生器电路，接收外部睡眠信号的睡眠引脚和耦合到时钟发生器电路和睡眠引脚的第一接口电路。时钟发生器电路响应于外部时钟信号产生核心时钟信号和总线时钟信号。当外部休眠信号被断言时，当核心时钟信号和总线时钟信号彼此处于第一预定关系时，处理器进入休眠状态。

8. 发明授权

US07023457B2 System and method for intensity control of a pixel 有权
公开(公告)号：US07023457B2
公开(公告)日：2006-04-04
申请号：US09805755
申请日：2001-03-13
申请人： Samson X. Huang , Ralph M. Kling
发明人： Samson X. Huang , Ralph M. Kling
IPC分类号： G09G5/10
CPC分类号： G09G3/3607 , G09G3/2022 , G09G3/2074 , G09G3/2081
摘要： An LCOS chip may have a pixel divided into an outer subpixel and an inner subpixel. A driver may independently drive the subpixels. The driving technique may be pulse-width modulation. Because of the pixel is divided into subpixels, pulses of short widths that drive an undivided pixel may be replaced with pulses of longer duration. In an alternative embodiment, the pixel is not divided into subpixels. The driving technique may be a combination of pulse width and pulse height modulation. The waveform may replace pulses of short widths with pulses of longer duration and reduced voltage levels.

9. 发明授权

US5621360A Voltage supply isolation buffer 失效
标题翻译：电压隔离缓冲器
公开(公告)号：US5621360A
公开(公告)日：1997-04-15
申请号：US510180
申请日：1995-08-02
申请人： Samson X. Huang
发明人： Samson X. Huang
IPC分类号： H03K3/03 , H03K3/3565 , H03K5/13 , H03K17/16 , H03L7/099 , H03B5/00
CPC分类号： H03K3/3565 , H03K17/161 , H03K3/03 , H03K5/133 , H03L7/0995
摘要： A CMOS delay cell with feedback circuitry to ensure that the delay cell is operating in saturation mode. A voltage controlled oscillator (VCO) comprising a loop of an odd number of delay cells, where the VCO is operating in a saturation mode. Under normal operation any intermediate node in the VCO will generate an output signal from a delay cell with reduced supply noise. The output signal can be used to generate a PLL clock signal with a lower phase jitter than prior art VCO's operating at low supply potentials.
摘要翻译：具有反馈电路的CMOS延迟单元，以确保延迟单元工作在饱和模式。包括奇数个延迟单元的环路的压控振荡器（VCO），其中VCO以饱和模式工作。在正常工作状态下，VCO中的任何中间节点将产生具有降低的电源噪声的延迟单元的输出信号。输出信号可用于产生具有比现有技术的VCO在低电源电位下操作更低的相位抖动的PLL时钟信号。

10. 发明授权

US5311475A High speed full and empty flag generators for first-in first-out memory 失效
标题翻译：用于先进先出存储器的高速全空和空标志发生器
公开(公告)号：US5311475A
公开(公告)日：1994-05-10
申请号：US692012
申请日：1991-04-26
申请人： Samson X. Huang
发明人： Samson X. Huang
IPC分类号： G06F5/10 , G06F5/14 , G11C7/00
CPC分类号： G06F5/14
摘要： A read signal and write signal for a FIFO each has a flag generating edge and a preceding edge. The read or write counter in an empty of full flag generator responds to the preceding edge of the read or write signal so that the empty or full comparator of the generator may generate an updated empty or full flag value before the onset of the flag generating edge. The empty or full flag generator also includes a gate and a pulse generating circuit. The pulse generating circuit responds to the flag generating edge by generating an enabling signal enabling the gate to pass the comparator output to a latch. When the empty or full comparator indicates that a FIFO is empty or full, the comparator output passed by the gate will force the output high, thereby asserting an empty flag or a full flag. The empty flag generator also includes a second pulse generating circuit which updates the empty flag signal to indicate a non-empty FIFO in response to each write signal. The full flag generator also includes a second pulse generating circuit which updates the full flag signal to indicate a non-full FIFO in response to each read signal.
摘要翻译： FIFO的读信号和写信号各具有标志生成边和前边。全空标志发生器的空的读或写计数器响应读或写信号的前沿，使得发生器的空或完全比较器可以在标志生成边缘开始之前产生更新的空标志或全标志值。空或全标志发生器还包括门和脉冲发生电路。脉冲发生电路通过产生启用信号使得栅极将比较器输出传递到锁存器来响应标志产生沿。当空或完整比较器指示FIFO为空或满时，由门通过的比较器输出将强制输出为高电平，从而断言空标志或满标志。空标志生成器还包括第二脉冲发生电路，其响应于每个写入信号更新空标志信号以指示非空FIFO。全标志发生器还包括第二脉冲发生电路，其响应于每个读取信号更新全标志信号以指示非完整FIFO。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式