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1. 发明授权

US09035309B2 3D CMOS image sensors, sensor systems including the same 有权
标题翻译： 3D CMOS图像传感器，传感器系统包括相同
公开(公告)号：US09035309B2
公开(公告)日：2015-05-19
申请号：US12984972
申请日：2011-01-05
申请人： Young-soo Park , Won-joo Kim , Kyoo-chul Cho , Gi-jung Kim , Sam-jong Choi
发明人： Young-soo Park , Won-joo Kim , Kyoo-chul Cho , Gi-jung Kim , Sam-jong Choi
IPC分类号： H01L27/146
CPC分类号： H01L27/14629 , H01L27/14687
摘要： A three-dimensional (3D) CMOS image sensor (CIS) that sufficiently absorbs incident infrared-rays (IRs) and includes an infrared-ray (IR) receiving unit formed in a thin epitaxial film, thereby being easily manufactured using a conventional CIS process, a sensor system including the 3D CIS, and a method of manufacturing the 3D CIS, the 3D CIS including an IR receiving part absorbing IRs incident thereto by repetitive reflection to produce electron-hole pairs (EHPs); and an electrode part formed on the IR receiving part and collecting electrons produced by applying a predetermined voltage thereto.
摘要翻译：一种三维（3D）CMOS图像传感器（CIS），其足以吸收入射的红外线（IR）并且包括形成在薄的外延膜中的红外线（IR）接收单元，由此容易地使用传统的CIS工艺包括3D CIS的传感器系统和制造3D CIS的方法，3D CIS包括通过重复反射吸收入射到其中的IR的IR接收部分以产生电子 - 空穴对（EHP）; 以及形成在IR接收部上并且收集通过施加预定电压而产生的电子的电极部分。

2. 发明授权

US08497570B2 Wafer, fabricating method of the same, and semiconductor substrate 失效
标题翻译：晶片，其制造方法和半导体衬底
公开(公告)号：US08497570B2
公开(公告)日：2013-07-30
申请号：US13178919
申请日：2011-07-08
申请人： Sun-Ha Hwang , Young-Soo Park , Sam-Jong Choi , Joon-Young Choi , Tae-Hyoung Koo
发明人： Sun-Ha Hwang , Young-Soo Park , Sam-Jong Choi , Joon-Young Choi , Tae-Hyoung Koo
IPC分类号： H01L29/36
CPC分类号： H01L21/3221 , H01L21/223 , H01L21/26513 , H01L29/78
摘要： A wafer, a fabricating method of the same, and a semiconductor substrate are provided. The wafer includes a first substrate layer formed at a first surface, a second substrate layer formed at a second surface opposite to the first surface, the second substrate layer having a greater oxygen concentration than the first substrate layer, and an oxygen diffusion protecting layer formed between the first substrate layer and the second substrate layer, the oxygen diffusion protecting layer being located closer to the first surface than to the second surface.
摘要翻译：提供晶片，其制造方法和半导体衬底。晶片包括形成在第一表面的第一基底层，形成在与第一表面相反的第二表面的第二基底层，第二基底层具有比第一基底层更大的氧浓度，以及形成氧扩散保护层在第一基板层和第二基板层之间，氧扩散保护层位于比第二表面更靠近第一表面的位置。

3. 发明申请

US20120056304A1 Wafer, Fabricating Method Of The Same, And Semiconductor Substrate 失效
标题翻译：晶圆，其制造方法及半导体基板
公开(公告)号：US20120056304A1
公开(公告)日：2012-03-08
申请号：US13178919
申请日：2011-07-08
申请人： Sun-Ha Hwang , Young-Soo Park , Sam-Jong Choi , Joon-Young Choi , Tae-Hyoung Koo
发明人： Sun-Ha Hwang , Young-Soo Park , Sam-Jong Choi , Joon-Young Choi , Tae-Hyoung Koo
IPC分类号： H01L29/02
CPC分类号： H01L21/3221 , H01L21/223 , H01L21/26513 , H01L29/78
摘要： A wafer, a fabricating method of the same, and a semiconductor substrate are provided. The wafer includes a first substrate layer formed at a first surface, a second substrate layer formed at a second surface opposite to the first surface, the second substrate layer having a greater oxygen concentration than the first substrate layer, and an oxygen diffusion protecting layer formed between the first substrate layer and the second substrate layer, the oxygen diffusion protecting layer being located closer to the first surface than to the second surface.
摘要翻译：提供晶片，其制造方法和半导体衬底。晶片包括形成在第一表面的第一基底层，形成在与第一表面相反的第二表面的第二基底层，第二基底层具有比第一基底层更大的氧浓度，以及形成氧扩散保护层在第一基板层和第二基板层之间，氧扩散保护层位于比第二表面更靠近第一表面的位置。

4. 发明申请

US20080014722A1 SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US20080014722A1
公开(公告)日：2008-01-17
申请号：US11775130
申请日：2007-07-09
申请人： Young-Soo PARK , Kyoo-Chul CHO , Hee-Sung KIM , Tae-Soo KANG , Sam-Jong CHOI
发明人： Young-Soo PARK , Kyoo-Chul CHO , Hee-Sung KIM , Tae-Soo KANG , Sam-Jong CHOI
IPC分类号： H01L21/20
CPC分类号： H01L21/76254 , H01L27/1207 , H01L27/1211 , H01L29/66795
摘要： Provided are a semiconductor device, and a method of forming the same. In one embodiment, the semiconductor device includes a semiconductor layer, first and second semiconductor fins, an insulating layer, and an inter-fin connection member. The first and second semiconductor fins are placed on the semiconductor layer, and have different crystal directions. The first semiconductor fin is connected to the semiconductor layer, and has the equivalent crystal direction as that of the semiconductor layer. The insulating layer is interposed between the second semiconductor fin and the semiconductor layer, and has an opening in which the first semiconductor fin is inserted. The inter-fin connection member connects the first semiconductor fin and the second semiconductor fin together on the insulating layer.
摘要翻译：提供半导体器件及其形成方法。在一个实施例中，半导体器件包括半导体层，第一和第二半导体鳍片，绝缘层和鳍间连接构件。第一和第二半导体散热片放置在半导体层上，具有不同的晶体方向。第一半导体鳍状物与半导体层连接，具有与半导体层相同的晶体方向。绝缘层介于第二半导体鳍片和半导体层之间，并且具有插入第一半导体鳍片的开口。翅片间连接构件将第一半导体翅片和第二半导体翅片在绝缘层上连接起来。

5. 发明授权

US07964907B2 Integrated circuit device gate structures 有权
标题翻译：集成电路器件门结构
公开(公告)号：US07964907B2
公开(公告)日：2011-06-21
申请号：US12468414
申请日：2009-05-19
申请人： Sam-jong Choi , Yong-kwon Kim , Kyoo-chul Cho , Kyung-soo Kim , Jae-ryong Jung , Tae-soo Kang , Sang-Sig Kim
发明人： Sam-jong Choi , Yong-kwon Kim , Kyoo-chul Cho , Kyung-soo Kim , Jae-ryong Jung , Tae-soo Kang , Sang-Sig Kim
IPC分类号： H01L21/00
CPC分类号： H01L21/28282 , B82Y10/00 , H01L29/42324 , H01L29/42332 , H01L29/792 , H01L29/7923
摘要： Methods of forming a gate structure for an integrated circuit memory device include forming a first dielectric layer having a dielectric constant of under 7 on an integrated circuit substrate. Ions of a selected element from group 4 of the periodic table and having a thermal diffusivity of less than about 0.5 centimeters per second (cm2/s) are injected into the first dielectric layer to form a charge storing region in the first dielectric layer with a tunnel dielectric layer under the charge storing region. A metal oxide second dielectric layer is formed on the first dielectric layer, the second dielectric layer. The substrate including the first and second dielectric layers is thermally treated to form a plurality of discrete charge storing nano crystals in the charge storing region and a gate electrode layer is formed on the second dielectric layer. Gate structures for integrated circuit devices and memory cells are also provided.
摘要翻译：形成用于集成电路存储器件的栅极结构的方法包括在集成电路衬底上形成具有低于7的介电常数的第一介电层。将元素周期表第4组的选定元素的离子注入到第一电介质层中，以在第一电介质层中形成电荷存储区，其中第一电介质层的电荷存储区域在电荷存储区域下的隧道介电层。金属氧化物第二电介质层形成在第一电介质层，第二电介质层上。包括第一和第二电介质层的衬底被热处理以在电荷存储区域中形成多个离散的电荷存储纳米晶体，并且在第二电介质层上形成栅极电极层。还提供用于集成电路器件和存储单元的栅极结构。

6. 发明申请

US20080246077A1 Method of fabricating semiconductor memory device and semiconductor memory device fabricated by the method 审中-公开
标题翻译：通过该方法制造半导体存储器件和半导体存储器件的方法
公开(公告)号：US20080246077A1
公开(公告)日：2008-10-09
申请号：US12012592
申请日：2008-02-04
申请人： Young-Soo Park , Sam-Jong Choi , Kyoo-Chul Cho , Tae-Soo Kang
发明人： Young-Soo Park , Sam-Jong Choi , Kyoo-Chul Cho , Tae-Soo Kang
IPC分类号： H01L27/108 , H01L21/425
CPC分类号： H01L29/7881 , B82Y10/00 , H01L21/26506 , H01L29/40114 , H01L29/42332
摘要： In a method for fabricating a semiconductor memory device and a semiconductor memory device fabricated by the method, the method includes forming a multi-layered dielectric structure including a first dielectric layer with an ion implantation layer and a second dielectric layer without an ion implantation layer, over a semiconductor substrate; forming nanocrystals in the first and second dielectric layers by diffusing ions of the ion implantation layer by thermally treating the multi-layered dielectric structure; and forming a gate electrode on the multi-layered dielectric structure.
摘要翻译：在通过该方法制造半导体存储器件和半导体存储器件的方法中，该方法包括形成包括具有离子注入层的第一介电层和没有离子注入层的第二电介质层的多层电介质结构，在半导体衬底上; 通过热处理多层电介质结构，通过离子注入层的离子扩散来在第一和第二电介质层中形成纳米晶体; 以及在所述多层电介质结构上形成栅电极。

7. 发明申请

US20070232041A1 Integrated circuit device gate structures having charge storing nano crystals in a metal oxide dielectric layer and methods of forming the same 审中-公开
标题翻译：在金属氧化物介电层中具有电荷存储纳米晶体的集成电路器件栅极结构及其形成方法
公开(公告)号：US20070232041A1
公开(公告)日：2007-10-04
申请号：US11510058
申请日：2006-08-25
申请人： Sam-jong Choi , Kyoo-chul Cho , Soo-yeol Choi , Yong-kwon Kim , Young-soo Park , Chan-kook In , Hae-jin Park , Sang-Sig Kim
发明人： Sam-jong Choi , Kyoo-chul Cho , Soo-yeol Choi , Yong-kwon Kim , Young-soo Park , Chan-kook In , Hae-jin Park , Sang-Sig Kim
IPC分类号： H01L21/3205
CPC分类号： H01L21/265 , B82Y10/00 , G11C2216/06 , H01L21/28167 , H01L21/28185 , H01L21/28194 , H01L29/1037 , H01L29/40114 , H01L29/42328 , H01L29/42332 , H01L29/42336 , H01L29/42368 , H01L29/513 , H01L29/517 , H01L29/6659 , H01L29/66825 , H01L29/7881 , H01L29/7885 , H01L29/7887
摘要： Methods of forming a gate structure for an integrated circuit memory device include forming a metal oxide dielectric layer on an integrated circuit substrate. Ions of a selected element from group 4 of the periodic table and having a thermal diffusivity of less than about 0.5 centimeters per second (cm2/s) are injected into the dielectric layer to form a charge storing region in the dielectric layer with a tunnel dielectric layer under the charge storing region and a capping dielectric layer above the charge storing region. The substrate including the metal oxide dielectric layer is thermally treated to form a plurality of discrete charge storing nano crystals in the charge storing region. A gate electrode layer is formed on the dielectric layer.
摘要翻译：形成用于集成电路存储器件的栅极结构的方法包括在集成电路衬底上形成金属氧化物介电层。将元素周期表第4组的选定元素的离子注入到电介质层中，并且具有小于约0.5厘米每秒（cm 2 / s）的热扩散率，形成电荷存储区在具有电荷存储区域下方的隧道介电层的电介质层和电荷存储区域上方的封盖电介质层。包含金属氧化物介电层的基板被热处理以在电荷存储区域中形成多个离散的电荷存储纳米晶体。在电介质层上形成栅极电极层。

8. 发明授权

US07550347B2 Methods of forming integrated circuit device gate structures 有权
标题翻译：形成集成电路器件门结构的方法
公开(公告)号：US07550347B2
公开(公告)日：2009-06-23
申请号：US11510059
申请日：2006-08-25
申请人： Sam-jong Choi , Yong-kwon Kim , Kyoo-chul Cho , Kyung-soo Kim , Jae-ryong Jung , Tae-soo Kang , Sang-Sig Kim
发明人： Sam-jong Choi , Yong-kwon Kim , Kyoo-chul Cho , Kyung-soo Kim , Jae-ryong Jung , Tae-soo Kang , Sang-Sig Kim
IPC分类号： H01L21/00
CPC分类号： H01L21/28282 , B82Y10/00 , H01L29/42324 , H01L29/42332 , H01L29/792 , H01L29/7923
摘要： Methods of forming a gate structure for an integrated circuit memory device include forming a first dielectric layer having a dielectric constant of under 7 on an integrated circuit substrate. Ions of a selected element from group 4 of the periodic table and having a thermal diffusivity of less than about 0.5 centimeters per second (cm2/s) are injected into the first dielectric layer to form a charge storing region in the first dielectric layer with a tunnel dielectric layer under the charge storing region. A metal oxide second dielectric layer is formed on the first dielectric layer, the second dielectric layer. The substrate including the first and second dielectric layers is thermally treated to form a plurality of discrete charge storing nano crystals in the charge storing region and a gate electrode layer is formed on the second dielectric layer. Gate structures for integrated circuit devices and memory cells are also provided.
摘要翻译：形成用于集成电路存储器件的栅极结构的方法包括在集成电路衬底上形成具有低于7的介电常数的第一介电层。将元素周期表第4组的选定元素的离子注入到第一电介质层中，以在第一电介质层中形成具有小于约0.5厘米每秒（cm 2 / s）的热扩散率的离子，从而在第一电介质层中形成电荷存储区，在电荷存储区域下的隧道介电层。金属氧化物第二电介质层形成在第一电介质层，第二电介质层上。包括第一和第二电介质层的衬底被热处理以在电荷存储区域中形成多个离散的电荷存储纳米晶体，并且在第二电介质层上形成栅极电极层。还提供用于集成电路器件和存储单元的栅极结构。

9. 发明授权

US07372150B2 Semiconductor wafer having identification indication 失效
标题翻译：具有识别指示的半导体晶片
公开(公告)号：US07372150B2
公开(公告)日：2008-05-13
申请号：US10684343
申请日：2003-10-10
申请人： Sam-Jong Choi , Gi-Jung Kim , Kyoo-Chul Cho , Yeon-Sook Kim , Shin-Hyeok Han , Hoe-Sik Chung
发明人： Sam-Jong Choi , Gi-Jung Kim , Kyoo-Chul Cho , Yeon-Sook Kim , Shin-Hyeok Han , Hoe-Sik Chung
IPC分类号： H01L23/04
CPC分类号： H01L23/544 , H01L29/0657 , H01L2223/54406 , H01L2223/54493 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor wafer including an identification indication is provided. The wafer includes a convex edge with an upper surface area and a lower surface area. The identification indication is in a marking region which is disposed on a lower side surface of the convex edge. The lower side surface has a wide region where the marking region is located. This wide region has a width that is wider than an upper side surface of the wafer and thus makes a cross-section of a side of the wafer asymmetrical. With the present invention, the entire top surface of the semiconductor wafer can be utilized for a semiconductor chip region and prevents manufacturing problems associated with the uneven nature of the identification indication when the identification is located on the top surface of the wafer.
摘要翻译：提供了包括识别指示的半导体晶片。晶片包括具有上表面区域和下表面区域的凸边缘。识别指示位于设置在凸缘的下侧表面上的标记区域中。下侧表面具有标记区域所在的宽区域。该宽区域的宽度比晶片的上侧面宽，因此晶片侧面的截面不对称。利用本发明，半导体晶片的整个顶表面可以用于半导体芯片区域，并且当识别位于晶片的顶表面上时，可防止与识别指示的不均匀性有关的制造问题。

10. 发明申请

US20070128846A1 Integrated circuit device gate structures and methods of forming the same 有权
标题翻译：集成电路器件栅极结构及其形成方法
公开(公告)号：US20070128846A1
公开(公告)日：2007-06-07
申请号：US11510059
申请日：2006-08-25
申请人： Sam-jong Choi , Yong-kwon Kim , Kyoo-chul Cho , Kyung-soo Kim , Jae-ryong Jung , Tae-soo Kang , Sang-Sig Kim
发明人： Sam-jong Choi , Yong-kwon Kim , Kyoo-chul Cho , Kyung-soo Kim , Jae-ryong Jung , Tae-soo Kang , Sang-Sig Kim
IPC分类号： H01L21/4763
CPC分类号： H01L21/28282 , B82Y10/00 , H01L29/42324 , H01L29/42332 , H01L29/792 , H01L29/7923
摘要： Methods of forming a gate structure for an integrated circuit memory device include forming a first dielectric layer having a dielectric constant of under 7 on an integrated circuit substrate. Ions of a selected element from group 4 of the periodic table and having a thermal diffusivity of less than about 0.5 centimeters per second (cm2/s) are injected into the first dielectric layer to form a charge storing region in the first dielectric layer with a tunnel dielectric layer under the charge storing region. A metal oxide second dielectric layer is formed on the first dielectric layer, the second dielectric layer. The substrate including the first and second dielectric layers is thermally treated to form a plurality of discrete charge storing nano crystals in the charge storing region and a gate electrode layer is formed on the second dielectric layer. Gate structures for integrated circuit devices and memory cells are also provided.
摘要翻译：形成用于集成电路存储器件的栅极结构的方法包括在集成电路衬底上形成具有低于7的介电常数的第一介电层。将元素周期表第4组的选定元素的离子注入到第一介电层中，并且具有小于约0.5厘米每秒（cm 2 / s）的热扩散率，从而形成电荷存储区域，在电荷存储区域下方具有隧道介电层。金属氧化物第二电介质层形成在第一电介质层，第二电介质层上。包括第一和第二电介质层的衬底被热处理以在电荷存储区域中形成多个离散的电荷存储纳米晶体，并且在第二电介质层上形成栅极电极层。还提供用于集成电路器件和存储单元的栅极结构。

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