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1. 发明授权

US08614634B2 8b/9b encoding for reducing crosstalk on a high speed parallel bus 有权
标题翻译： 8b / 9b编码，用于降低高速并行总线上的串扰
公开(公告)号：US08614634B2
公开(公告)日：2013-12-24
申请号：US13442772
申请日：2012-04-09
申请人： Sunil Sudhakaran , Russell R. Newcomb
发明人： Sunil Sudhakaran , Russell R. Newcomb
IPC分类号： H03M5/00
CPC分类号： H04L25/14 , G06F13/42 , H04L25/4908
摘要： Systems and methods for encoding/decoding a data word using an 8b/9b encoding scheme that eliminates two-aggressor crosstalk are disclosed. The 8b/9b encoding scheme enables a data word to be encoded using code words. Each of the valid code words does not include any three consecutive bits having a logic level of logic-high (i.e., ‘1’), and represent transition vectors for consecutive symbols transmitted over the high speed parallel bus. An encoder and corresponding decoder are disclosed for implementing the 8b/9b encoding scheme. In one embodiment, the encoder/decoder implements a modified Fibonacci sequence algorithm. In another embodiment, the encoder/decoder implements a look-up table.
摘要翻译：公开了使用消除双侵略性串扰的8b / 9b编码方案对数据字进行编码/解码的系统和方法。 8b / 9b编码方案使得能够使用代码字对数据字进行编码。每个有效代码字不包括具有逻辑高逻辑电平（即'1'）的任何三个连续位，并且表示用于通过高速并行总线传输的连续符号的转移向量。公开了一种用于实现8b / 9b编码方案的编码器和相应的解码器。在一个实施例中，编码器/解码器实现修改的斐波纳契序列算法。在另一个实施例中，编码器/解码器实现查找表。

2. 发明授权

US07519892B1 Binary data encoding/decoding with error detection, such as for communicating between computing platform components 有权
标题翻译：具有错误检测的二进制数据编码/解码，例如用于计算平台组件之间的通信
公开(公告)号：US07519892B1
公开(公告)日：2009-04-14
申请号：US11251405
申请日：2005-10-14
申请人： Russell R. Newcomb , William B. Simms , Barry A. Wagner
发明人： Russell R. Newcomb , William B. Simms , Barry A. Wagner
IPC分类号： H03M13/00
CPC分类号： H03M13/51
摘要： Embodiments for binary encoding and/or decoding data are disclosed. In or more embodiments, N data bits may be encoded using one of a plurality of codes derived from at least N+1 bits wherein each of the plurality of codes comprises approximately equal numbers of bits at a first logical level and a second logical level.
摘要翻译：公开了用于二进制编码和/或解码数据的实施例。在一个或多个实施例中，可以使用从至少N + 1个比特得到的多个代码中的一个代码对N个数据比特进行编码，其中多个代码中的每一个在第一逻辑等级和第二逻辑等级包括大致相等数量的比特。

3. 发明授权

US08812892B1 Hardware WCK2CK training engine using meta-EDC sweeping and adjustably accurate voting algorithm for clock phase detection 有权
标题翻译：硬件WCK2CK培训引擎采用meta-EDC扫描和可调精确的投票算法进行时钟相位检测
公开(公告)号：US08812892B1
公开(公告)日：2014-08-19
申请号：US12650242
申请日：2009-12-30
申请人： Eric Lyell Hill , Russell R. Newcomb , Shu-Yi Yu
发明人： Eric Lyell Hill , Russell R. Newcomb , Shu-Yi Yu
IPC分类号： G06F1/12 , G06F1/10
CPC分类号： G06F1/10
摘要： One embodiment of the present invention sets forth a technique for performing high-performance clock training. One clock training sweep operation is performed to determine phase relationships for two write clocks with respect to a command clock. The phase relationships are generated to satisfy timing requirements for two different client devices, such as GDDR5 DRAM components. A second clock training sweep operation is performed to better align local clocks operating on the client devices. A voting tally is maintained during the second clock training sweep to record phase agreement at each step in the clock training sweep. The voting tally then determines whether one of the local clocks should be inverted to better align the two local clocks.
摘要翻译：本发明的一个实施例提出了一种用于执行高性能时钟训练的技术。执行一个时钟训练扫描操作以确定相对于命令时钟的两个写入时钟的相位关系。生成相位关系以满足两种不同客户端设备（如GDDR5 DRAM组件）的时序要求。执行第二时钟训练扫描操作以更好地对准在客户端设备上操作的本地时钟。在第二次时钟训练扫描期间保持投票记录，以在时钟训练扫描的每个步骤记录相位协议。然后，投票计数确定是否应将本地时钟之一反转以更好地对准两个本地时钟。

4. 发明申请

US20130266046A1 8B/9B Encoding For Reducing Crosstalk on a High Speed Parallel Bus 有权
标题翻译： 8B / 9B用于减少高速并行总线上的串扰的编码
公开(公告)号：US20130266046A1
公开(公告)日：2013-10-10
申请号：US13442772
申请日：2012-04-09
申请人： Sunil SUDHAKARAN , Russell R. Newcomb
发明人： Sunil SUDHAKARAN , Russell R. Newcomb
IPC分类号： H04B15/00 , H04B1/38 , H04B1/02
CPC分类号： H04L25/14 , G06F13/42 , H04L25/4908
摘要： Systems and methods for encoding/decoding a data word using an 8b/9b encoding scheme that eliminates two-aggressor crosstalk are disclosed. The 8b/9b encoding scheme enables a data word to be encoded using code words. Each of the valid code words does not include any three consecutive bits having a logic level of logic-high (i.e., ‘1’), and represent transition vectors for consecutive symbols transmitted over the high speed parallel bus. An encoder and corresponding decoder are disclosed for implementing the 8b/9b encoding scheme. In one embodiment, the encoder/decoder implements a modified Fibonacci sequence algorithm. In another embodiment, the encoder/decoder implements a look-up table.
摘要翻译：公开了使用消除双侵略性串扰的8b / 9b编码方案对数据字进行编码/解码的系统和方法。 8b / 9b编码方案使得能够使用代码字对数据字进行编码。每个有效代码字不包括具有逻辑高逻辑电平（即'1'）的任何三个连续位，并且表示用于通过高速并行总线传输的连续符号的转移向量。公开了一种用于实现8b / 9b编码方案的编码器和相应的解码器。在一个实施例中，编码器/解码器实现修改的斐波纳契序列算法。在另一个实施例中，编码器/解码器实现查找表。

5. 发明授权

US08489911B1 Hardware WCK2CK training engine using meta-EDC sweeping and adjustably accurate voting algorithm for clock phase detection 有权
标题翻译：硬件WCK2CK培训引擎采用meta-EDC扫描和可调精确的投票算法进行时钟相位检测
公开(公告)号：US08489911B1
公开(公告)日：2013-07-16
申请号：US12650281
申请日：2009-12-30
申请人： Eric Lyell Hill , Russell R. Newcomb , Shu-Yi Yu
发明人： Eric Lyell Hill , Russell R. Newcomb , Shu-Yi Yu
IPC分类号： G06F1/12 , G06F1/10
CPC分类号： G06F1/10
摘要： One embodiment of the present invention sets forth a technique for performing high-performance clock training. One clock training sweep operation is performed to determine phase relationships for two write clocks with respect to a command clock. The phase relationships are generated to satisfy timing requirements for two different client devices, such as GDDR5 DRAM components. A second clock training sweep operation is performed to better align local clocks operating on the client devices. A voting tally is maintained during the second clock training sweep to record phase agreement at each step in the clock training sweep. The voting tally then determines whether one of the local clocks should be inverted to better align the two local clocks.
摘要翻译：本发明的一个实施例提出了一种用于执行高性能时钟训练的技术。执行一个时钟训练扫描操作以确定相对于命令时钟的两个写入时钟的相位关系。生成相位关系以满足两种不同客户端设备（如GDDR5 DRAM组件）的时序要求。执行第二时钟训练扫描操作以更好地对准在客户端设备上操作的本地时钟。在第二次时钟训练扫描期间保持投票记录，以在时钟训练扫描的每个步骤记录相位协议。然后，投票计数确定是否应将本地时钟之一反转以更好地对准两个本地时钟。

6. 发明授权

US07603246B2 Data interface calibration 有权
标题翻译：数据接口校准
公开(公告)号：US07603246B2
公开(公告)日：2009-10-13
申请号：US11394951
申请日：2006-03-31
申请人： Russell R. Newcomb , Barry A. Wagner
发明人： Russell R. Newcomb , Barry A. Wagner
IPC分类号： G06F19/00
CPC分类号： G06F13/4243 , H04L7/0004 , H04L7/0091 , H04L7/033
摘要： Embodiments for positioning transitions in one or more data signals in relation to a data strobe signal are disclosed. For an example embodiment, a receiving device may return a test value to a transmitting device. Timing for one or more data signals may be adjusted in relation to a clock signal according, at least in part, to the test value returned from a receiving device.
摘要翻译：公开了相对于数据选通信号在一个或多个数据信号中定位转换的实施例。对于示例性实施例，接收设备可以将测试值返回给发送设备。至少部分地基于从接收装置返回的测试值，可以相对于时钟信号调整一个或多个数据信号的定时。

7. 发明授权

US4668936A Untrimmed 12 bit monotonic all capacitive A to D converter 失效
标题翻译：未调整的12位单调全电容A到D转换器
公开(公告)号：US4668936A
公开(公告)日：1987-05-26
申请号：US787831
申请日：1985-10-15
申请人： Russell R. Newcomb , William C. Black
发明人： Russell R. Newcomb , William C. Black
IPC分类号： H03M1/38 , H03M1/00 , H03M1/14 , H03M1/46 , H03M1/68 , H03M1/80
CPC分类号： H03M1/144 , H03M1/46 , H03M1/687 , H03M1/804 , H03M1/806
摘要： An M-bit all-capacitive analog-to-digital (A/D) converter is disclosed which includes 2.sup.N switched capacitors of substantially identical capacitance for use in determining the N most significant bits. Each of the capacitors have one terminal connected to a common node and its other terminal switchable to either ground or a positive reference voltage. At the beginning of a conversion cycle, the common node is at a potential indicative of a sampled analog input voltage, a first group of 2.sup.N-1 capacitors are switched to ground, and a second group of 2.sup.N-1 capacitors are switched to the positive reference voltage. For a given conversion cycle, selected capacitors of one of the capacitor groups are sequentially switched to drive the common node voltage to ground. A method is also disclosed for converting analog signals to digital signals utilizing parallel capacitive elements of substantially identical capacitance.
摘要翻译：公开了一种M位全电容模数（A / D）转换器，其包括用于确定N个最高有效位的基本相同电容的2N个开关电容器。每个电容器具有连接到公共节点的一个端子，并且其另一个端子可切换到接地或正参考电压。在转换周期开始时，公共节点处于指示采样的模拟输入电压的电位，第一组2N-1个电容器被切换到地，而第二组2N-1个电容器被切换到正的参考电压。对于给定的转换周期，顺序地切换电容器组中的一个的所选电容器以将公共节点电压驱动到地。还公开了一种利用基本上相同的电容的并联电容元件将模拟信号转换成数字信号的方法。

8. 发明授权

US08638241B2 8b/9b decoding for reducing crosstalk on a high speed parallel bus 有权
标题翻译： 8b / 9b解码，以减少高速并行总线上的串扰
公开(公告)号：US08638241B2
公开(公告)日：2014-01-28
申请号：US13443754
申请日：2012-04-10
申请人： Sunil Sudhakaran , Russell R. Newcomb
发明人： Sunil Sudhakaran , Russell R. Newcomb
IPC分类号： H03M5/00
CPC分类号： H04L25/14 , G06F13/42 , H04L25/4908
摘要： Systems and methods for encoding a data word using an 8b/9b encoding scheme that eliminates two-aggressor crosstalk are disclosed. The 8b/9b encoding scheme enables a data word that can be subdivided into portions of eight bits or less to be encoded using code words having one extra bit than the corresponding portion of the data word. Each of the valid code words does not include any three consecutive bits having a logic level of logic-high (i.e., ‘1’), and represent transition vectors for consecutive symbols transmitted over the high speed parallel bus. An encoder and corresponding decoder are disclosed for implementing the 8b/9b encoding scheme. In one embodiment, the encoder/decoder implements a modified Fibonacci sequence algorithm. In another embodiment, the encoder/decoder implements a look-up table. In some embodiments, data words may be less than eight bits wide.
摘要翻译：公开了使用消除双侵略性串扰的8b / 9b编码方案对数据字进行编码的系统和方法。 8b / 9b编码方案使得可以将可以被细分为8位或更少的部分的数据字使用具有比数据字的相应部分多一个位的码字进行编码。每个有效代码字不包括具有逻辑高逻辑电平（即'1'）的任何三个连续位，并且表示用于通过高速并行总线传输的连续符号的转移向量。公开了一种用于实现8b / 9b编码方案的编码器和相应的解码器。在一个实施例中，编码器/解码器实现修改的斐波纳契序列算法。在另一个实施例中，编码器/解码器实现查找表。在一些实施例中，数据字可以小于8位宽。

9. 发明申请

US20130266047A1 8B/9B DECODING FOR REDUCING CROSSTALK ON A HIGH SPEED PARALLEL BUS 有权
标题翻译： 8B / 9B解码用于降低高速并联总线上的CROSSTALK
公开(公告)号：US20130266047A1
公开(公告)日：2013-10-10
申请号：US13443754
申请日：2012-04-10
申请人： Sunil SUDHAKARAN , Russell R. NEWCOMB
发明人： Sunil SUDHAKARAN , Russell R. NEWCOMB
IPC分类号： H03D1/04 , H04B1/38
CPC分类号： H04L25/14 , G06F13/42 , H04L25/4908
摘要： Systems and methods for encoding a data word using an 8b/9b encoding scheme that eliminates two-aggressor crosstalk are disclosed. The 8b/9b encoding scheme enables a data word that can be subdivided into portions of eight bits or less to be encoded using code words having one extra bit than the corresponding portion of the data word. Each of the valid code words does not include any three consecutive bits having a logic level of logic-high (i.e., ‘1’), and represent transition vectors for consecutive symbols transmitted over the high speed parallel bus. An encoder and corresponding decoder are disclosed for implementing the 8b/9b encoding scheme. In one embodiment, the encoder/decoder implements a modified Fibonacci sequence algorithm. In another embodiment, the encoder/decoder implements a look-up table. In some embodiments, data words may be less than eight bits wide.
摘要翻译：公开了使用消除双侵略性串扰的8b / 9b编码方案对数据字进行编码的系统和方法。 8b / 9b编码方案使得可以将可以被细分为8位或更少的部分的数据字使用具有比数据字的相应部分多一个位的码字进行编码。每个有效代码字不包括具有逻辑高逻辑电平（即'1'）的任何三个连续位，并且表示用于通过高速并行总线传输的连续符号的转移向量。公开了一种用于实现8b / 9b编码方案的编码器和相应的解码器。在一个实施例中，编码器/解码器实现修改的斐波纳契序列算法。在另一个实施例中，编码器/解码器实现查找表。在一些实施例中，数据字可以小于8位宽。

10. 发明授权

US08095762B1 Low latency synchronous memory performance switching with drift refresh 有权
标题翻译：具有漂移刷新功能的低延迟同步存储器性能切换
公开(公告)号：US08095762B1
公开(公告)日：2012-01-10
申请号：US11690007
申请日：2007-03-22
申请人： Hans Wolfgang Schulze , Russell R. Newcomb , Barry A. Wagner
发明人： Hans Wolfgang Schulze , Russell R. Newcomb , Barry A. Wagner
IPC分类号： G06F12/00
CPC分类号： G06F1/324 , G06F1/3275 , G11C7/1066 , G11C7/1093 , G11C7/222 , Y02D10/126 , Y02D10/14
摘要： A synchronous memory device is configured to switch into and out of a full speed mode to change speed the speed of data transactions without significantly disturbing the frequency of a clock input to a PLL or DLL that provides the internal clock for the synchronous memory device. Since the PLL or DLL receives a clock signal whether or not the synchronous memory device is in a non-full speed mode, the PLL or DLL does not need to settle or relock when the clock signal is reapplied to exit a different speed mode and return to the full speed mode. Therefore, the latency incurred to switch into and out of different speed modes is reduced by eliminating or substantially reducing the time for settling or relocking the PLL or DLL.
摘要翻译：同步存储器设备被配置为切换到全速模式以切换数据事务的速度，而不会明显地扰乱向同步存储器件提供内部时钟的PLL或DLL的时钟输入的频率。由于PLL或DLL接收到时钟信号，无论同步存储器件是否处于非全速模式，当重新应用时钟信号以退出不同的速度模式并返回时，PLL或DLL不需要稳定或重新锁定到全速模式。因此，通过消除或显着减少用于建立或重新锁定PLL或DLL的时间，减少了切换和转出不同速度模式的延迟。

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