专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20110131372A1 OPTIMIZING SEGMENT ACCESS IN BINARY TRANSLATION 有权
标题翻译：在二进制翻译中优化部门访问
公开(公告)号：US20110131372A1
公开(公告)日：2011-06-02
申请号：US12629682
申请日：2009-12-02
申请人： Ross Charles KNIPPEL , Jeffrey W. SHELDON , Ole AGESEN
发明人： Ross Charles KNIPPEL , Jeffrey W. SHELDON , Ole AGESEN
IPC分类号： G06F12/08
CPC分类号： G06F9/45516 , G06F9/45558 , G06F2009/45583
摘要： A mechanism for a binary translator to emit code that will pre-generate information about a memory segment when a segment selector is assigned to a segment register. The binary translator emits code that will be executed when a memory access using that segment register is encountered and the emitted code will access the pre-generated information when evaluating the memory access request. Memory accesses, where a number of bytes being accessed is less than or equal to a predetermined value, are validated with a minimal number of steps in the code emitted by the binary translator.
摘要翻译：一种二进制转换器发出代码的机制，当段选择器被分配给段寄存器时，该代码将预先生成关于存储器段的信息。二进制翻译器发出将在遇到使用该段寄存器的存储器访问时执行的代码，并且当评估存储器访问请求时，发出的代码将访问预生成的信息。存储器访问，其中访问的字节数小于或等于预定值，以二进制翻译器发出的代码中的最小步数进行验证。

2. 发明授权

US06401137B1 Method, apparatus, and article of manufacture for processing a virtual call in a multi-threaded program 失效
标题翻译：在多线程程序中处理虚拟呼叫的方法，装置和制品
公开(公告)号：US06401137B1
公开(公告)日：2002-06-04
申请号：US09106879
申请日：1998-06-30
申请人： Mario Iwan Wolczko , Ross Charles Knippel
发明人： Mario Iwan Wolczko , Ross Charles Knippel
IPC分类号： G06F954
CPC分类号： G06F9/52 , G06F9/4491
摘要： Methods, systems, and articles of manufacture consistent with the present invention process a virtual call during execution of a multi-threaded program by ensuring that the steps of patching the virtual call to the appropriate method are performed within a single instruction cycle. This prevents other threads from executing instructions related to the virtual call in the middle of the patching procedure. Methods, systems, and articles of manufacture consistent with the present invention identify a target, such as a targeted method and a class of a receiver object, associated with the virtual call and then determine an address identifier, such as a memory address pointer to the class of the receiver object. By ensuring that the address identifier is within a restricted address space, a predetermined boundary of the memory storage device can be used to patch the call to the identified target and patch the address identifier for the identified target to the correct address identifier within a single instruction cycle.
摘要翻译：符合本发明的方法，系统和制品在执行多线程程序期间通过确保在单个指令周期内执行对适当方法的虚拟调用进行补丁的步骤来处理虚拟调用。这可以防止其他线程在修补过程中间执行与虚拟调用相关的指令。与本发明一致的方法，系统和制品符合识别与虚拟呼叫相关联的目标，例如目标方法和接收者对象的类别，然后确定地址标识符，诸如存储器地址指针接收器对象的类。通过确保地址标识符在受限地址空间内，可以使用存储器存储设备的预定边界来修改对所识别的目标的呼叫，并将所识别的目标的地址标识符修补到单个指令内的正确的地址标识符周期。

3. 发明授权

US08316193B2 Optimizing segment access in binary translation 有权
标题翻译：优化二进制翻译中的段访问
公开(公告)号：US08316193B2
公开(公告)日：2012-11-20
申请号：US12629682
申请日：2009-12-02
申请人： Ross Charles Knippel , Jeffrey W. Sheldon , Ole Agesen
发明人： Ross Charles Knippel , Jeffrey W. Sheldon , Ole Agesen
IPC分类号： G06F12/00
CPC分类号： G06F9/45516 , G06F9/45558 , G06F2009/45583
摘要： A mechanism for a binary translator to emit code that will pre-generate information about a memory segment when a segment selector is assigned to a segment register. The binary translator emits code that will be executed when a memory access using that segment register is encountered and the emitted code will access the pre-generated information when evaluating the memory access request. Memory accesses, where a number of bytes being accessed is less than or equal to a predetermined value, are validated with a number of steps in the code emitted by the binary translator.
摘要翻译：一种二进制转换器发出代码的机制，当段选择器被分配给段寄存器时，该代码将预先生成关于存储器段的信息。二进制翻译器发出将在遇到使用该段寄存器的存储器访问时执行的代码，并且当评估存储器访问请求时，发出的代码将访问预生成的信息。存储器访问（其中访问的字节数小于或等于预定值）通过二进制翻译器发出的代码中的多个步骤来验证。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式