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1. 发明授权

US5923574A Optimized, combined leading zeros counter and shifter 失效
标题翻译：优化的，组合的前导零和移位器
公开(公告)号：US5923574A
公开(公告)日：1999-07-13
申请号：US716591
申请日：1996-09-18
申请人： Roland Albert Bechade
发明人： Roland Albert Bechade
IPC分类号： G06F5/01 , G06F7/74
CPC分类号： G06F7/74 , G06F5/012
摘要： By combining a count leading zero circuit with a bit shifter in a digital processor though detection of groups of leading zeros prior to completion of counting of leading zeros, shifting for normalization and number format conversion can concurrently be initiated and partially carried out prior to completion of a determination of the number of leading zeros in an expression of a number. The combined count leading zero circuit and shifter provides faster operation which can be completed within one cycle time and hardware architecture simplifications are achieved to reduce required circuit element count and chip space.
摘要翻译：通过在数字处理器中组合计数前导零电路与位移器，通过在完成前导零的计数之前检测前导零组，可以在完成前后零序同步启动和部分执行移位确定数字表达式中前导零的数量。组合计数引导零电路和移位器提供更快的操作，可以在一个周期内完成，并且实现硬件架构简化以减少所需的电路元件数量和芯片空间。

2. 发明授权

US5745744A High speed mask generation using selection logic 失效
标题翻译：使用选择逻辑的高速掩码生成
公开(公告)号：US5745744A
公开(公告)日：1998-04-28
申请号：US542478
申请日：1995-10-12
申请人： Roland Albert Bechade
发明人： Roland Albert Bechade
IPC分类号： G06F7/76 , G06F7/00
CPC分类号： G06F7/764 , G06F7/49952
摘要： In a mask generator, decoders are provided for decoding respective portions of an input bit string into an intermediate string, and first and second selection signals. The intermediate string is placed into a first mask by a primary selection stage according to the first selection signals. The first mask is placed into a second mask by a secondary selection stage according to the second selection signals. The decoders are implemented using combinational logic, and the primary selectors are implemented using multiplexer and phase inverter circuits. Sixteen bit mask generation is realized from a 4-bit input string using only two decoders and a primary selector. Sixty-four bit mask generation is realized using a 6-bit input bit string and a secondary selector. The first and second masks contain two contiguous series of 1s and 0s. Parallel arrangements of mask generators are disclosed so that alternating series of 1s and 0s can be placed in output masks. Masks of arbitrary lengths can be produced using additional decoding and selectors.
摘要翻译：在掩码生成器中，提供解码器用于将输入位串的各个部分解码为中间串，以及第一和第二选择信号。根据第一选择信号，通过初级选择级将中间串置入第一掩模。根据第二选择信号，通过次级选择级将第一掩模放入第二掩模。解码器使用组合逻辑实现，并且主选择器使用多路复用器和相位逆变器电路实现。仅使用两个解码器和主选择器的4位输入串实现了16位掩码生成。使用6位输入位串和次级选择器实现了64位位掩码生成。第一个和第二个掩码包含两个连续的1s和0s系列。公开了掩模发生器的平行布置，使得1s和0s的交替系列可以放置在输出掩模中。可以使用附加的解码和选择器来产生任意长度的掩码。

3. 发明授权

US5789966A Distributed multiplexer 失效
标题翻译：分布式多路复用器
公开(公告)号：US5789966A
公开(公告)日：1998-08-04
申请号：US715654
申请日：1996-09-18
申请人： Roland Albert Bechade
发明人： Roland Albert Bechade
IPC分类号： H03K17/693 , H03K19/173 , H03K17/16
CPC分类号： H03K17/693 , H03K19/1737
摘要： Signal propagation time through a transmission gate array or multiplexer is significantly reduced and output signal transition time is halved by detecting non-selection of a section of the multiplexer and activating an output circuit, preferably in the form of a logic gate, to respond to a signal passed through a selected section of the transmission gate array or multiplexer. Specifically, upon non-selection of a section, an appropriate logic-valued signal at a reference voltage is propagated on an internal node of the multiplexer to the input of the output circuit to precondition or activate the output circuit. Since this signal is strongly tied to the reference voltage, the response of the output circuit is improved in both response time and transition time. Further, capacitance of internal nodes of the multiplexer is insulated or isolated from the inputs to the multiplexer, avoiding trade-offs between circuit performance and wiring congestion.
摘要翻译：通过传输门阵列或多路复用器的信号传播时间显着减少，并且通过检测多路复用器的一部分的非选择并且优选地以逻辑门的形式激活输出电路来响应于一个传输门阵列或多路复用器的信号传播时间信号通过传输门阵列或多路复用器的选定部分。具体来说，在不选择一个部分时，在参考电压下的适当的逻辑值信号在多路复用器的内部节点上传播到输出电路的输入端以预处理或激活输出电路。由于该信号与参考电压密切相关，所以在响应时间和转换时间两方面，输出电路的响应都得到了改善。此外，多路复用器的内部节点的电容与多路复用器的输入绝缘或隔离，避免了电路性能与布线拥塞之间的权衡。

4. 发明授权

US5841683A Least significant bit and guard bit extractor 失效
标题翻译：最低有效位和保护位提取器
公开(公告)号：US5841683A
公开(公告)日：1998-11-24
申请号：US718272
申请日：1996-09-20
申请人： Roland Albert Bechade , Robert Hayosh , Stephen Gerard Shuma
发明人： Roland Albert Bechade , Robert Hayosh , Stephen Gerard Shuma
IPC分类号： G06F7/57 , G06F7/76 , G06F5/01
CPC分类号： G06F7/764 , G06F7/483 , G06F7/49952
摘要： In connection with a logic circuit including a mask generator for determining a value for a so-called "sticky bit" in a binary number to be truncated and rounded, an intermediate signal is taken from the mask generator and an Exclusive-OR function applied to adjacent bits to generate a second mask containing or adjacent to a transition between the portion of the number to be dropped and the portion to be retained in the truncated number. The second mask is applied to different overlapping groups of bits in a portion of the number which contains the least significant bit and the guard bit as determined from the number of bits to be dropped, for example, by shifting out from a shifter, as the number is truncated and rounded to extract a specific bit in each group of bits. By extracting such specific bits using a mask, the extraction process is removed from the critical path of the processor which includes the shifter and the extraction process can proceed in parallel with the shifting process.
摘要翻译：结合包括掩模发生器的逻辑电路，用于确定要截断和舍入的二进制数中所谓的“粘性位”的值，从掩码发生器获取中间信号，并将异或功能应用于相邻位以产生包含或相邻待丢弃数量的部分与要保留在截断数中的部分之间的转换的第二掩码。第二掩码被应用于数字的不同的重叠组，其中包含最低有效位和保护位，例如通过从移位器移出，从被丢弃的位的数量确定，作为数字被截断并舍入，以提取每组位中的特定位。通过使用掩码提取这样的特定比特，提取处理从包括移位器的处理器的关键路径中移除，并且提取处理可以与移位处理并行进行。

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