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1. 发明授权

US10486057B2 Competitive escape rooms 有权
公开(公告)号：US10486057B2
公开(公告)日：2019-11-26
申请号：US15710818
申请日：2017-09-20
申请人： Dallin Henrie , Robert Strain
发明人： Dallin Henrie , Robert Strain
IPC分类号： A63F9/00 , A63J5/02 , A63F9/24 , A63F11/00 , A63J3/00
CPC分类号： A63F9/0078 , A63F9/24 , A63J5/02 , A63F2009/2442 , A63F2011/0095 , A63F2250/00 , A63J3/00
摘要： Apparatuses, systems, methods, and computer program products are presented for competitive escape rooms. A first room has a predetermined method to accomplish a task within the first room. A second room has a same predetermined method to accomplish a same task within the second room as in a first room. A hardware controller device determines in which of a first room and a second room a task is completed first by one of a plurality of competing sets of users.

2. 发明授权

US08247840B2 Apparatus and method for improved leakage current of silicon on insulator transistors using a forward biased diode 有权
标题翻译：使用正向偏置二极管改善绝缘体上硅晶体管的漏电流的装置和方法
公开(公告)号：US08247840B2
公开(公告)日：2012-08-21
申请号：US12348797
申请日：2009-01-05
申请人： Ashok Kumar Kapoor , Robert Strain
发明人： Ashok Kumar Kapoor , Robert Strain
IPC分类号： H01L29/66
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/0629 , H01L29/66636 , H01L29/7833 , H03K19/0005 , H03K19/0016 , H03K19/00361
摘要： Use of a forward biased diode to reduce leakage current of transistors implemented on silicon on insulator (SOI) is a particular challenge due to the difficulty of achieving effective contact with the region beneath the gate of the transistor. An improved implementation in SOI gate fingers that reach under the source through tunnels that are contacted with a region outside the transistor. A further embodiment uses drain extension implants to provide good channel connection.
摘要翻译：使用正向偏置二极管来减少在绝缘体上硅（SOI）上实现的晶体管的泄漏电流是一个特别的挑战，因为难以实现与晶体管栅极之下的区域的有效接触。通过与晶体管外部的区域接触的隧道在源极下方的SOI栅极指中的改进的实现。另一实施例使用漏极延伸植入物来提供良好的通道连接。

3. 发明申请

US20180078848A1 COMPETITIVE ESCAPE ROOMS 审中-公开
公开(公告)号：US20180078848A1
公开(公告)日：2018-03-22
申请号：US15710818
申请日：2017-09-20
申请人： DALLIN HENRIE , ROBERT STRAIN
发明人： DALLIN HENRIE , ROBERT STRAIN
IPC分类号： A63F9/00 , A63J5/02
CPC分类号： A63F9/0078 , A63F9/24 , A63F2009/2442 , A63F2011/0095 , A63F2250/00 , A63J3/00 , A63J5/02
摘要： Apparatuses, systems, methods, and computer program products are presented for competitive escape rooms. A first room has a predetermined method to accomplish a task within the first room. A second room has a same predetermined method to accomplish a same task within the second room as in a first room. A hardware controller device determines in which of a first room and a second room a task is completed first by one of a plurality of competing sets of users.

4. 发明授权

US07863689B2 Apparatus for using a well current source to effect a dynamic threshold voltage of a MOS transistor 有权
标题翻译：用于使用井电流源来实现MOS晶体管的动态阈值电压的装置
公开(公告)号：US07863689B2
公开(公告)日：2011-01-04
申请号：US12348809
申请日：2009-01-05
申请人： Robert Strain
发明人： Robert Strain
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/0629 , H01L27/0727 , H01L27/1203 , H01L29/47 , H01L29/78 , H01L29/872
摘要： Deep submicron wells of MOS transistors, implemented over an ungrounded well, exhibit two modes of operation: a current sink mode and a current source mode. While operation as a current sink is well understood and successfully controlled, it is also necessary to control the current provided in the current source mode of the well. A Schottky diode is connected between the well and the gate, the Schottky diode having a smaller barrier height than that of the PN junction of the well-to-source. For an NMOS transistor, current flows through the PN junction when the gate is high. When the gate is low, current flows through the Schottky diode. This difference of current flow results in a difference in transistor threshold, thereby achieving a dynamic threshold voltage using the current from the well when operating at the current source mode.
摘要翻译：在非接地井上实现的MOS晶体管的深亚微米阱具有两种工作模式：电流吸收模式和电流源模式。当作为电流吸收器的操作被很好地理解并成功地控制时，还需要控制在井的当前源模式中提供的电流。肖特基二极管连接在阱和栅极之间，肖特基二极管的栅极高度高于源阱的PN结的势垒高度。对于NMOS晶体管，当栅极为高电平时，电流流过PN结。当栅极低时，电流流过肖特基二极管。电流的这种差异导致晶体管阈值的差异，从而当在当前源模式下工作时，使用来自阱的电流实现动态阈值电压。

5. 发明申请

US20100134182A1 Apparatus and Method for Improving Drive-Strength and Leakage of Deep Submicron MOS Transistors 有权
标题翻译：提高深亚微米MOS晶体管的驱动强度和泄漏的装置和方法
公开(公告)号：US20100134182A1
公开(公告)日：2010-06-03
申请号：US12701896
申请日：2010-02-08
申请人： Ashok Kumar KAPOOR , Robert Strain , Reuven Marko
发明人： Ashok Kumar KAPOOR , Robert Strain , Reuven Marko
IPC分类号： G05F3/02 , H01L21/8238
CPC分类号： H01L27/0629 , H01L27/0727 , H01L27/1203 , H01L29/78 , H03K19/0005 , H03K19/0016 , H03K19/00361
摘要： An apparatus and method of manufacture for metal-oxide semiconductor (MOS) transistors is disclosed. Devices in accordance with the invention are operable at voltages below 2V. The devices are area efficient, have improved drive strength, and have reduced leakage current. A dynamic threshold voltage control scheme comprised of a forward biased diode in parallel with a capacitor is used, implemented without changing the existing MOS technology process. This scheme controls the threshold voltage of each transistor. In the OFF state, the magnitude of the threshold voltage of the transistor increases, keeping the transistor leakage to a minimum. In the ON state, the magnitude of the threshold voltage decreases, resulting in increased drive strength. The invention is particularly useful in MOS technology for both bulk and silicon on insulator (SOI) CMOS. The use of reverse biasing of the well, in conjunction with the above construct to further decrease leakage in a MOS transistor, is also shown.
摘要翻译：公开了一种用于金属氧化物半导体（MOS）晶体管的装置和制造方法。根据本发明的装置可在低于2V的电压下工作。这些器件具有区域有效性，具有改进的驱动强度，并且具有减小的漏电流。使用包括与电容器并联的正向偏置二极管的动态阈值电压控制方案，而不改变现有的MOS技术过程。该方案控制每个晶体管的阈值电压。在OFF状态下，晶体管的阈值电压的大小增加，保持晶体管漏电量最小。在ON状态下，阈值电压的大小减小，导致驱动强度增加。本发明在用于体积和绝缘体上硅（SOI）CMOS的MOS技术中特别有用。还示出了与上述结构一起使用阱的反向偏置以进一步减小MOS晶体管中的泄漏。

6. 发明授权

US08048732B2 Method for reducing leakage current and increasing drive current in a metal-oxide semiconductor (MOS) transistor 有权
标题翻译：减少金属氧化物半导体（MOS）晶体管中漏电流和增加驱动电流的方法
公开(公告)号：US08048732B2
公开(公告)日：2011-11-01
申请号：US12701896
申请日：2010-02-08
申请人： Ashok Kumar Kapoor , Robert Strain , Reuven Marko
发明人： Ashok Kumar Kapoor , Robert Strain , Reuven Marko
IPC分类号： H01L21/8238
CPC分类号： H01L27/0629 , H01L27/0727 , H01L27/1203 , H01L29/78 , H03K19/0005 , H03K19/0016 , H03K19/00361
摘要： An apparatus and method of manufacture for metal-oxide semiconductor (MOS) transistors is disclosed. Devices in accordance with the invention are operable at voltages below 2V. The devices are area efficient, have improved drive strength, and have reduced leakage current. A dynamic threshold voltage control scheme comprised of a forward biased diode in parallel with a capacitor is used, implemented without changing the existing MOS technology process. This scheme controls the threshold voltage of each transistor. In the OFF state, the magnitude of the threshold voltage of the transistor increases, keeping the transistor leakage to a minimum. In the ON state, the magnitude of the threshold voltage decreases, resulting in increased drive strength. The invention is particularly useful in MOS technology for both bulk and silicon on insulator (SOI) CMOS. The use of reverse biasing of the well, in conjunction with the above construct to further decrease leakage in a MOS transistor, is also shown.
摘要翻译：公开了一种用于金属氧化物半导体（MOS）晶体管的装置和制造方法。根据本发明的装置可在低于2V的电压下工作。这些器件具有区域有效性，具有改进的驱动强度，并且具有减小的漏电流。使用包括与电容器并联的正向偏置二极管的动态阈值电压控制方案，而不改变现有的MOS技术过程。该方案控制每个晶体管的阈值电压。在OFF状态下，晶体管的阈值电压的大小增加，保持晶体管漏电量最小。在ON状态下，阈值电压的大小减小，导致驱动强度增加。本发明在用于体积和绝缘体上硅（SOI）CMOS的MOS技术中特别有用。还示出了与上述结构一起使用阱的反向偏置以进一步减小MOS晶体管中的泄漏。

7. 发明申请

US20090174464A1 APPARATUS AND METHOD FOR IMPROVED LEAKAGE CURRENT OF SILICON ON INSULATOR TRANSISTORS USING A FORWARD BIASED DIODE 有权
标题翻译：使用前向偏置二极管改善绝缘体晶体管上硅的漏电流的装置和方法
公开(公告)号：US20090174464A1
公开(公告)日：2009-07-09
申请号：US12348797
申请日：2009-01-05
申请人： Ashok Kumar Kapoor , Robert Strain
发明人： Ashok Kumar Kapoor , Robert Strain
IPC分类号： H03K3/01 , H01L27/12 , H01L21/8238 , H01L21/336
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/0629 , H01L29/66636 , H01L29/7833 , H03K19/0005 , H03K19/0016 , H03K19/00361
摘要： Use of a forward biased diode to reduce leakage current of transistors implemented on silicon on insulator (SOI) is a particular challenge due to the difficulty of achieving effective contact with the region beneath the gate of the transistor. An improved implementation in SOI gate fingers that reach under the source through tunnels that are contacted with a region outside the transistor. A further embodiment uses drain extension implants to provide good channel connection.
摘要翻译：使用正向偏置二极管来减少在绝缘体上硅（SOI）上实现的晶体管的泄漏电流是一个特别的挑战，因为难以实现与晶体管栅极之下的区域的有效接触。通过与晶体管外部的区域接触的隧道在源极下方的SOI栅极指中的改进的实现。另一实施例使用漏极延伸植入物来提供良好的通道连接。

8. 发明申请

US20090152770A1 MECHANICALLY COLLAPSIBLE CORE FOR INJECTION MOLDING 审中-公开
标题翻译：机械可塑性注射成型芯
公开(公告)号：US20090152770A1
公开(公告)日：2009-06-18
申请号：US12187916
申请日：2008-08-07
申请人： PAUL ROBERT MIKAC , DALE ROBERT STRAIN
发明人： PAUL ROBERT MIKAC , DALE ROBERT STRAIN
IPC分类号： B29C45/40
CPC分类号： B29C45/4421
摘要： The invention relates to a mechanically-collapsible core device includes a central pin having a plurality of engaging members, a plurality of first collapsible core members each having an engaging member that engages with a respective engaging member of the central pin, a base member having a plurality of engaging members, and a plurality of second collapsible core members each having an engaging member that engages with a respective engaging member of the base member. The pin is retracted from a home position, thereby causing the first core members to collapse inward. The base member is then retracted, thereby causing the second core members to translate inward and linearly. The result is that the core device collapses inward in size so as to permit the device to be removed from the inside of a molded article.
摘要翻译：本发明涉及一种机械可折叠的芯装置，其包括具有多个接合构件的中心销，多个第一可收缩芯构件，每个具有与中心销的相应接合构件接合的接合构件，基座构件具有多个接合构件和多个第二可收缩芯体，每个具有接合构件，所述接合构件与所述基座构件的相应接合构件接合。销从原始位置缩回，从而使第一芯构件向内折叠。然后使基部构件缩回，从而使第二芯构件向内和向内平移。其结果是，核心装置的尺寸向内收缩，从而允许装置从模制品的内部移除。

9. 发明申请

US20070229145A1 Method and Apparatus for Dynamic Threshold Voltage Control of MOS Transistors in Dynamic Logic Circuits 有权
标题翻译：用于动态逻辑电路中MOS晶体管的动态阈值电压控制的方法和装置
公开(公告)号：US20070229145A1
公开(公告)日：2007-10-04
申请号：US11684466
申请日：2007-03-09
申请人： Ashok Kapoor , Robert Strain , Reuven Marko
发明人： Ashok Kapoor , Robert Strain , Reuven Marko
IPC分类号： H03K3/01
CPC分类号： H03K19/0963 , H01L21/823807 , H01L27/0727 , H01L27/0921
摘要： Metal-oxide semiconductor (MOS) transistors that are operable at voltages below 1.5V, that are area efficient, and that exhibit improved drive strength and leakage current that are disclosed. A dynamic threshold voltage control scheme is used that does not require a change to existing MOS technology processes. Threshold voltage of the transistor is controlled, such that in the Off state, the threshold voltage of the transistor is set high, keeping the transistor leakage to a small value. The advantages provided by apply to dynamic logic, as well as in the specific well separation imposed by design rules because well potential difference are lower than the supply voltage swing.
摘要翻译：可在低于1.5V的电压下工作的金属氧化物半导体（MOS）晶体管，其面积效率高，并且表现出改进的驱动强度和漏电流。使用动态阈值电压控制方案，其不需要改变现有的MOS技术过程。控制晶体管的阈值电压，使得在关断状态下，晶体管的阈值电压被设置为高，从而将晶体管泄漏保持在较小的值。动态逻辑提供的优点，以及设计规则施加的具体井分离，因为潜在电位差低于电源电压摆幅。

10. 发明申请

US20090206380A1 APPARATUS AND METHOD FOR USING A WELL CURRENT SOURCE TO EFFECT A DYNAMIC THRESHOLD VOLTAGE OF A MOS TRANSISTOR 有权
标题翻译：使用良好的电流源来影响MOS晶体管的动态阈值电压的装置和方法
公开(公告)号：US20090206380A1
公开(公告)日：2009-08-20
申请号：US12348809
申请日：2009-01-05
申请人： Robert Strain
发明人： Robert Strain
IPC分类号： H01L27/06 , H01L21/8234
CPC分类号： H01L27/0629 , H01L27/0727 , H01L27/1203 , H01L29/47 , H01L29/78 , H01L29/872
摘要： Deep submicron wells of MOS transistors, implemented over an ungrounded well, exhibit two modes of operation: a current sink mode and a current source mode. While operation as a current sink is well understood and successfully controlled, it is also necessary to control the current provided in the current source mode of the well. A Schottky diode is connected between the well and the gate, the Schottky diode having a smaller barrier height than that of the PN junction of the well-to-source. For an NMOS transistor, current flows through the PN junction when the gate is high. When the gate is low, current flows through the Schottky diode. This difference of current flow results in a difference in transistor threshold, thereby achieving a dynamic threshold voltage using the current from the well when operating at the current source mode.
摘要翻译：在非接地井上实现的MOS晶体管的深亚微米阱具有两种工作模式：电流吸收模式和电流源模式。当作为电流吸收器的操作被很好地理解并成功地控制时，还需要控制在井的当前源模式中提供的电流。肖特基二极管连接在阱和栅极之间，肖特基二极管的栅极高度高于源阱的PN结的势垒高度。对于NMOS晶体管，当栅极为高电平时，电流流过PN结。当栅极低时，电流流过肖特基二极管。电流的这种差异导致晶体管阈值的差异，从而当在当前源模式下工作时，使用来自阱的电流实现动态阈值电压。

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