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1. 发明授权

US06799264B2 Memory accelerator for ARM processor pre-fetching multiple instructions from cyclically sequential memory partitions 有权
标题翻译： ARM处理器的内存加速器从循环顺序的内存分区预取多个指令
公开(公告)号：US06799264B2
公开(公告)日：2004-09-28
申请号：US09788691
申请日：2001-02-20
申请人： Gregory K Goodhue , Ata R Khan , John H. Wharton , Robert Michael Kallal
发明人： Gregory K Goodhue , Ata R Khan , John H. Wharton , Robert Michael Kallal
IPC分类号： G06F906
CPC分类号： G06F9/3814 , G06F9/3802 , G06F9/381
摘要： A memory accelerator module buffers program instructions and/or data for high speed access using a deterministic access protocol. The program memory is logically partitioned into ‘stripes’, or ‘cyclically sequential’ partitions, and the memory accelerator module includes a latch that is associated with each partition. When a particular partition is accessed, it is loaded into its corresponding latch, and the instructions in the next sequential partition are automatically pre-fetched into their corresponding latch. In this manner, the performance of a sequential-access process will have a known response, because the pre-fetched instructions from the next partition will be in the latch when the program sequences to these instructions. Previously accessed blocks remain in their corresponding latches until the pre-fetch process ‘cycles around’ and overwrites the contents of each sequentially-accessed latch. In this manner, the performance of a loop process, with regard to memory access, will be determined based solely on the size of the loop. If the loop is below a given size, it will be executable without overwriting existing latches, and therefore will not incur memory access delays as it repeatedly executes instructions contained within the latches. If the loop is above a given size, it will overwrite existing latches containing portions of the loop, and therefore require subsequent re-loadings of the latch with each loop. Because the pre-fetch is automatic, and determined solely on the currently accessed instruction, the complexity and overhead associated with this memory acceleration is minimal.
摘要翻译：存储器加速器模块使用确定性访问协议来缓冲用于高速访问的程序指令和/或数据。程序存储器在逻辑上被划分为“条带”或“循环顺序”分区，并且存储器加速器模块包括与每个分区相关联的锁存器。当访问特定分区时，它被加载到其对应的锁存器中，并且下一个顺序分区中的指令被自动预取到其对应的锁存器中。以这种方式，顺序访问过程的性能将具有已知的响应，因为当程序对这些指令进行排序时，来自下一分区的预取指令将在锁存器中。先前访问的块保留在其对应的锁存器中，直到预取处理“周转”并覆盖每个顺序访问的锁存器的内容。以这种方式，关于存储器访问的循环处理的执行将仅基于循环的大小来确定。如果循环低于一个给定的大小，它将可执行而不会覆盖现有的锁存器，因此它不会因为重复执行包含在锁存器内的指令而引起存储器访问延迟。如果循环高于给定尺寸，它将覆盖包含循环部分的现有锁存器，因此需要随后每个循环重新加载锁存器。因为预取是自动的，并且仅根据当前访问的指令确定，与该存储器加速相关联的复杂性和开销是最小的。

2. 发明授权

US07290119B2 Memory accelerator with two instruction set fetch path to prefetch second set while executing first set of number of instructions in access delay to instruction cycle ratio 有权
标题翻译：存储器加速器具有两条指令集提取路径，用于在访问延迟到指令周期比率的同时执行第一组指令数时预取第二组
公开(公告)号：US07290119B2
公开(公告)日：2007-10-30
申请号：US10923284
申请日：2004-08-20
申请人： Gregory K. Goodhue , Ata R. Khan , John H. Wharton , Robert Michael Kallal
发明人： Gregory K. Goodhue , Ata R. Khan , John H. Wharton , Robert Michael Kallal
IPC分类号： G06F9/28
CPC分类号： G06F9/3814 , G06F9/3802 , G06F9/381
摘要： A memory accelerator module buffers program instructions and/or data for high speed access using a deterministic access protocol. The program memory is logically partitioned into ‘stripes’, or ‘cyclically sequential’ partitions, and the memory accelerator module includes a latch that is associated with each partition. When a particular partition is accessed, it is loaded into its corresponding latch, and the instructions in the next sequential partition are automatically pre-fetched into their corresponding latch. In this manner, the performance of a sequential-access process will have a known response, because the pre-fetched instructions from the next partition will be in the latch when the program sequences to these instructions. Previously accessed blocks remain in their corresponding latches until the pre-fetch process ‘cycles around’ and overwrites the contents of each sequentially-accessed latch. In this manner, the performance of a loop process, with regard to memory access, will be determined based solely on the size of the loop. If the loop is below a given size, it will be executable without overwriting existing latches, and therefore will not incur memory access delays as it repeatedly executes instructions contained within the latches. If the loop is above a given size, it will overwrite existing latches containing portions of the loop, and therefore require subsequent re-loadings of the latch with each loop. Because the pre-fetch is automatic, and determined solely on the currently accessed instruction, the complexity and overhead associated with this memory acceleration is minimal.
摘要翻译：存储器加速器模块使用确定性访问协议来缓冲用于高速访问的程序指令和/或数据。程序存储器在逻辑上被划分为“条带”或“循环顺序”分区，并且存储器加速器模块包括与每个分区相关联的锁存器。当访问特定分区时，它被加载到其对应的锁存器中，并且下一个顺序分区中的指令被自动预取到其对应的锁存器中。以这种方式，顺序访问过程的性能将具有已知的响应，因为当程序对这些指令进行排序时，来自下一分区的预取指令将在锁存器中。先前访问的块保留在其对应的锁存器中，直到预取处理“周转”并覆盖每个顺序访问的锁存器的内容。以这种方式，关于存储器访问的循环处理的执行将仅基于循环的大小来确定。如果循环低于一个给定的大小，它将可执行而不会覆盖现有的锁存器，因此它不会因为重复执行包含在锁存器内的指令而引起存储器访问延迟。如果循环高于给定尺寸，它将覆盖包含循环部分的现有锁存器，因此需要随后每个循环重新加载锁存器。因为预取是自动的，并且仅根据当前访问的指令确定，与该存储器加速相关联的复杂性和开销是最小的。

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