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1. 发明授权

US08547760B2 Memory access alignment in a double data rate (‘DDR’) system 有权
标题翻译：双数据速率（“DDR”）系统中的存储器访问对齐
公开(公告)号：US08547760B2
公开(公告)日：2013-10-01
申请号：US13171811
申请日：2011-06-29
申请人： Steven K. Jenkins , Robert B. Likovich, Jr. , Michael R. Trombley
发明人： Steven K. Jenkins , Robert B. Likovich, Jr. , Michael R. Trombley
IPC分类号： G11C8/18
CPC分类号： G06F3/0605 , G06F3/0659 , G06F3/0673 , G06F12/00 , G11C7/1066 , G11C7/1072 , G11C7/1093 , G11C11/40 , G11C11/40622 , G11C29/022 , G11C29/023 , G11C29/028 , G11C2207/2254 , G11C2207/2272
摘要： Memory access alignment in a double data rate (‘DDR’) system, including: executing, by a memory controller, one or more write operations to a predetermined address of a DDR memory module, including sending to the DDR memory module a predetermined amount of data of a predetermined pattern along with a data strobe signal; executing, by the memory controller, a plurality of read operations from the predetermined address of the DDR memory module, including capturing data transmitted from the DDR memory module; and determining, by the memory controller, a read adjust value and a write adjust value in dependence upon the data captured in response to the read operations.
摘要翻译：在双数据速率（“DDR”）系统中的存储器访问对准，包括：由存储器控制器执行对DDR存储器模块的预定地址的一个或多个写入操作，包括向DDR存储器模块发送预定量的预定图案的数据以及数据选通信号; 由所述存储器控制器执行来自所述DDR存储器模块的预定地址的多个读取操作，包括捕获从所述DDR存储器模块发送的数据; 以及由存储器控制器根据读取操作所捕获的数据确定读取调整值和写入调整值。

2. 发明申请

US20130003475A1 Memory Access Alignment In A Double Data Rate ('DDR') System 有权
标题翻译：双数据速率（“DDR”）系统中的内存访问对齐
公开(公告)号：US20130003475A1
公开(公告)日：2013-01-03
申请号：US13171811
申请日：2011-06-29
申请人： Steven K. Jenkins , Robert B. Likovich, JR. , Michael R. Trombley
发明人： Steven K. Jenkins , Robert B. Likovich, JR. , Michael R. Trombley
IPC分类号： G11C8/18
CPC分类号： G06F3/0605 , G06F3/0659 , G06F3/0673 , G06F12/00 , G11C7/1066 , G11C7/1072 , G11C7/1093 , G11C11/40 , G11C11/40622 , G11C29/022 , G11C29/023 , G11C29/028 , G11C2207/2254 , G11C2207/2272
摘要： Memory access alignment in a double data rate (‘DDR’) system, including: executing, by a memory controller, one or more write operations to a predetermined address of a DDR memory module, including sending to the DDR memory module a predetermined amount of data of a predetermined pattern along with a data strobe signal; executing, by the memory controller, a plurality of read operations from the predetermined address of the DDR memory module, including capturing data transmitted from the DDR memory module; and determining, by the memory controller, a read adjust value and a write adjust value in dependence upon the data captured in response to the read operations.
摘要翻译：包括：由存储器控制器对DDR存储器模块的预定地址执行一个或多个写入操作，包括向DDR存储器模块发送预定量的数据的数据预定模式以及数据选通信号; 由所述存储器控制器执行来自所述DDR存储器模块的预定地址的多个读取操作，包括捕获从所述DDR存储器模块发送的数据; 以及由存储器控制器根据读取操作所捕获的数据确定读取调整值和写入调整值。

3. 发明授权

US07461364B2 Methods and readable media for using relative positioning in structures with dynamic ranges 有权
标题翻译：在具有动态范围的结构中使用相对定位的方法和可读介质
公开(公告)号：US07461364B2
公开(公告)日：2008-12-02
申请号：US11279237
申请日：2006-04-10
申请人： Charles L. Alley , Robert B. Likovich, Jr. , Joseph D. Mendenhall , Chad E. Winemiller
发明人： Charles L. Alley , Robert B. Likovich, Jr. , Joseph D. Mendenhall , Chad E. Winemiller
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： Methods and readable media for using relative positioning of items or components in a structure with dynamic ranges, such as an elastic I/O bus design for an Integrated Circuit (IC), are disclosed. Embodiments may include a user-defined type module having user-defined types representing relative instance positions within a structure. Embodiments may also include a translation helper module to receive information associated with a hierarchy and to return location information associated with the hierarchy and a translation module to translate between a specific location and a relative position of the instance based on one or more user-defined types and location information returned from the translation helper module to generate a list of translated results. Further embodiments of the translation module may include a relative position determiner to translate specific locations to relative positions and may also include a specific location determiner to translate relative positions to specific locations.
摘要翻译：公开了用于使物品或部件在具有动态范围的结构中的相对定位的方法和可读介质，例如用于集成电路（IC）的弹性I / O总线设计。实施例可以包括具有表示结构内的相对实例位置的用户定义类型的用户定义类型模块。实施例还可以包括翻译帮助器模块，用于接收与层级相关联的信息并返回与层级相关联的位置信息，以及翻译模块，用于基于一个或多个用户定义的类型在实例的特定位置和相对位置之间进行转换和从翻译助手模块返回的位置信息以生成翻译结果的列表。翻译模块的其他实施例可以包括将特定位置转换为相对位置的相对位置确定器，并且还可以包括将相对位置转换为特定位置的特定位置确定器。

4. 发明授权

US08212588B2 Opportunistic bus access latency 失效
标题翻译：机会总线访问延迟
公开(公告)号：US08212588B2
公开(公告)日：2012-07-03
申请号：US12729455
申请日：2010-03-23
申请人： Theodore P. Haggis , Robert B. Likovich, Jr. , James A. Mossman , Tiffany Tamaddoni-Jahromi , Robert B. Tremaine
发明人： Theodore P. Haggis , Robert B. Likovich, Jr. , James A. Mossman , Tiffany Tamaddoni-Jahromi , Robert B. Tremaine
IPC分类号： H03K19/094
CPC分类号： G06F13/4243
摘要： A bus system that includes a plurality of signal driving devices coupled to a common signal bus, a bus controlled circuit coupled to the common signal bus, and a compare circuit. The plurality of signal driving devices include a first signal driving device and a second signal driving device. The bus controller includes delay compensation circuitry with a configurable delay for each of the signal driving devices. The delay compensation circuitry has a current delay chain configuration associated with the first signal driving device. The compare circuit is configured to compare a first configurable delay associated with a first signal driving device to a second configurable delay associated with a second signal driving device of the plurality of signal driving devices, and for generating an output responsive to the comparing that indicates if the current delay chain configuration can be used by the second signal driving device.
摘要翻译：一种总线系统，其包括耦合到公共信号总线的多个信号驱动装置，耦合到公共信号总线的总线控制电路和比较电路。多个信号驱动装置包括第一信号驱动装置和第二信号驱动装置。总线控制器包括具有用于每个信号驱动装置的可配置延迟的延迟补偿电路。延迟补偿电路具有与第一信号驱动装置相关联的电流延迟链配置。比较电路被配置为将与第一信号驱动装置相关联的第一可配置延迟与与多个信号驱动装置中的第二信号驱动装置相关联的第二可配置延迟进行比较，并且用于响应于比较来产生响应于指示是否当前延迟链配置可以由第二信号驱动装置使用。

5. 发明授权

US08196111B2 Buckets of commands in a multiprocessor-based verification environment 失效
标题翻译：基于多处理器的验证环境中的各种命令
公开(公告)号：US08196111B2
公开(公告)日：2012-06-05
申请号：US11972690
申请日：2008-01-11
申请人： David M. Atoji , Ruchi Chandra , Robert B. Likovich, Jr.
发明人： David M. Atoji , Ruchi Chandra , Robert B. Likovich, Jr.
IPC分类号： G06F9/44
CPC分类号： G06F11/263
摘要： The present invention provides a method and system for providing a legal sequential combination of commands for verification testing of a computer system. Executable test commands are used to form sequentially ordered “buckets” of commands, wherein each bucket command sequence is legal under at least one rule. The buckets may be arranged in any sequential order, wherein a composite command sequence of the combined commands remains legal under the at least one rule. A further advantage of the invention is that wait/noop commands may be inserted within and between the buckets, extending the testing capabilities of the present invention into corner cases.
摘要翻译：本发明提供了一种用于提供用于计算机系统的验证测试的命令的合法顺序组合的方法和系统。可执行测试命令用于形成顺序排列的命令“桶”，其中每个桶命令序列在至少一个规则下是合法的。桶可以以任何顺序排列，其中组合命令的复合命令序列在至少一个规则下保持合法。本发明的另一个优点是可以将等待/ noop命令插入到桶内和桶之间，从而将本发明的测试能力扩展到角箱。

6. 发明申请

US20110234259A1 OPPORTUNISTIC BUS ACCESS LATENCY 失效
标题翻译：机场总线访问延迟
公开(公告)号：US20110234259A1
公开(公告)日：2011-09-29
申请号：US12729455
申请日：2010-03-23
申请人： Theodore P. Haggis , Robert B. Likovich, JR. , James A. Mossman , Tiffany Tamaddoni-Jahromi , Robert B. Tremaine
发明人： Theodore P. Haggis , Robert B. Likovich, JR. , James A. Mossman , Tiffany Tamaddoni-Jahromi , Robert B. Tremaine
IPC分类号： H03K19/0175
CPC分类号： G06F13/4243
摘要： A bus system that includes a plurality of signal driving devices coupled to a common signal bus, a bus controlled circuit coupled to the common signal bus, and a compare circuit. The plurality of signal driving devices include a first signal driving device and a second signal driving device. The bus controller includes delay compensation circuitry with a configurable delay for each of the signal driving devices. The delay compensation circuitry has a current delay chain configuration associated with the first signal driving device. The compare circuit is configured to compare a first configurable delay associated with a first signal driving device to a second configurable delay associated with a second signal driving device of the plurality of signal driving devices, and for generating an output responsive to the comparing that indicates if the current delay chain configuration can be used by the second signal driving device.
摘要翻译：一种总线系统，其包括耦合到公共信号总线的多个信号驱动装置，耦合到公共信号总线的总线控制电路和比较电路。多个信号驱动装置包括第一信号驱动装置和第二信号驱动装置。总线控制器包括具有用于每个信号驱动装置的可配置延迟的延迟补偿电路。延迟补偿电路具有与第一信号驱动装置相关联的电流延迟链配置。比较电路被配置为将与第一信号驱动装置相关联的第一可配置延迟与与多个信号驱动装置中的第二信号驱动装置相关联的第二可配置延迟进行比较，并且用于响应于比较来产生响应于指示是否当前延迟链配置可以由第二信号驱动装置使用。

7. 发明申请

US20090089728A1 SYSTEMS FOR USING RELATIVE POSITIONING IN STRUCTURES WITH DYNAMIC RANGES 失效
标题翻译：在具有动态范围的结构中使用相对定位的系统
公开(公告)号：US20090089728A1
公开(公告)日：2009-04-02
申请号：US12253481
申请日：2008-10-17
申请人： Charles L. Alley , Robert B. Likovich, JR. , Joseph D. Mendenhall , Chad E. Winemiller
发明人： Charles L. Alley , Robert B. Likovich, JR. , Joseph D. Mendenhall , Chad E. Winemiller
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： Systems for using relative positioning of items or components in a structure with dynamic ranges, such as an elastic I/O bus design for an Integrated Circuit (IC), are disclosed. Embodiments may include a user-defined type module having user-defined types representing relative instance positions within a structure. Embodiments may also include a translation helper module to receive information associated with a hierarchy and to return location information associated with the hierarchy and a translation module to translate between a specific location and a relative position of the instance based on one or more user-defined types and location information returned from the translation helper module to generate a list of translated results. Further embodiments of the translation module may include a relative position determiner to translate specific locations to relative positions and may also include a specific location determiner to translate relative positions to specific locations.
摘要翻译：公开了在具有动态范围的结构中使用项目或部件的相对定位的系统，例如用于集成电路（IC）的弹性I / O总线设计。实施例可以包括具有表示结构内的相对实例位置的用户定义类型的用户定义类型模块。实施例还可以包括翻译帮助器模块，用于接收与层级相关联的信息并返回与层级相关联的位置信息，以及翻译模块，用于基于一个或多个用户定义的类型在实例的特定位置和相对位置之间进行转换和从翻译助手模块返回的位置信息以生成翻译结果的列表。翻译模块的其他实施例可以包括将特定位置转换为相对位置的相对位置确定器，并且还可以包括将相对位置转换为特定位置的特定位置确定器。

8. 发明授权

US07398515B2 Buckets of commands in a multiprocessor-based verification environment 失效
标题翻译：基于多处理器的验证环境中的各种命令
公开(公告)号：US07398515B2
公开(公告)日：2008-07-08
申请号：US10620472
申请日：2003-07-16
申请人： David M. Atoji , Ruchi Chandra , Robert B. Likovich, Jr.
发明人： David M. Atoji , Ruchi Chandra , Robert B. Likovich, Jr.
IPC分类号： G06F9/44
CPC分类号： G06F11/263
摘要： The present invention provides a method and system for providing a legal sequential combination of commands for verification testing of a computer system. Executable test commands are used to form sequentially ordered “buckets” of commands, wherein each bucket command sequence is legal under at least one rule. The buckets may be arranged in any sequential order, wherein a composite command sequence of the combined commands remains legal under the at least one rule. A further advantage of the invention is that wait/noop commands may be inserted within and between the buckets, extending the testing capabilities of the present invention into corner cases.
摘要翻译：本发明提供了一种用于提供用于计算机系统的验证测试的命令的合法顺序组合的方法和系统。可执行测试命令用于形成顺序排列的命令“桶”，其中每个桶命令序列在至少一个规则下是合法的。桶可以以任何顺序排列，其中组合命令的复合命令序列在至少一个规则下保持合法。本发明的另一个优点是可以将等待/ noop命令插入到桶内和桶之间，从而将本发明的测试能力扩展到角箱。

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