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1. 发明授权

US07711993B2 JTAGchain bus switching and configuring device 失效
标题翻译： JTAG串行总线切换和配置设备
公开(公告)号：US07711993B2
公开(公告)日：2010-05-04
申请号：US12251257
申请日：2008-10-14
申请人： Mike Conrad Duron , Robert Allan Faust , Forrest Clifton Gray , Ajay Kumar Mahajan , Glenn Rueban Miles
发明人： Mike Conrad Duron , Robert Allan Faust , Forrest Clifton Gray , Ajay Kumar Mahajan , Glenn Rueban Miles
IPC分类号： G06F11/00
CPC分类号： G01R31/318558 , G01R31/318544 , G01R31/318555 , G06F13/4022
摘要： A JTAG bus cross point switching device that is commanded by the same bus which it configures. In a preferred embodiment a JTAG chain includes a cross point switching device that is capable of adding, omitting, or rearranging devices on a JTAG bus. The switching device itself is controlled by commands on the JTAG bus which it configures.
摘要翻译：一个JTAG总线交叉点交换设备，由其配置的同一总线指令。在优选实施例中，JTAG链包括能够在JTAG总线上添加，省略或重新排列设备的交叉点交换设备。开关设备本身由配置的JTAG总线上的命令控制。

2. 发明授权

US07498801B2 Apparatus, method, and computer program product for monitoring and controlling a microcomputer using a single existing pin 失效
标题翻译：用于使用单个现有销监视和控制微型计算机的装置，方法和计算机程序产品
公开(公告)号：US07498801B2
公开(公告)日：2009-03-03
申请号：US12029913
申请日：2008-02-12
申请人： Robert Allan Faust
发明人： Robert Allan Faust
IPC分类号： G01R31/00
CPC分类号： H04L25/4902 , H04L5/1423 , H04L25/4906
摘要： A method, apparatus, and computer program product are disclosed for monitoring and controlling a device using only one input/output (I/O) communication pin of the device. The pin is configured to be used to both transmit and receive data. Logical ones are generated using pulses that are a first length and logical zeros are generated using pulses that are a second length. The device is communicated with utilizing the generated logical ones and generated logical zeros by transmitting the logical ones and zeros to the device, and receiving the logical ones and zeros from the device utilizing the single I/O pin.
摘要翻译：公开了用于仅使用该设备的一个输入/输出（I / O）通信引脚来监视和控制设备的方法，装置和计算机程序产品。引脚被配置为用于发送和接收数据。使用作为第一长度的脉冲生成逻辑1，并且使用作为第二长度的脉冲来生成逻辑0。通过将逻辑1和0发送到设备，并利用单个I / O引脚从设备接收逻辑1和0来传送利用生成的逻辑1和产生的逻辑0的设备。

3. 发明授权

US07477176B2 Method and apparatus for generating multiple analog signals using a single microcontroller output pin 有权
标题翻译：使用单个微控制器输出引脚产生多个模拟信号的方法和装置
公开(公告)号：US07477176B2
公开(公告)日：2009-01-13
申请号：US11191641
申请日：2005-07-28
申请人： Robert Allan Faust , John Daniel Upton
发明人： Robert Allan Faust , John Daniel Upton
IPC分类号： H03M1/66
CPC分类号： G06F1/025
摘要： A method and apparatus are disclosed for generating multiple separate analog signals using a single microcontroller output pin. The microcontroller generates a waveform that is used to concurrently generate multiple separate analog signals. The microcontroller outputs a waveform that includes a first signal from one of the microcontroller's output pins. The first signal is used to produce a first analog signal. The microcontroller then outputs a delineating signal, as part of the waveform, from the microcontroller's output pin. The delineating signal indicates the start of a next signal in the waveform. The microcontroller then outputs a second signal, as part of the waveform, from its output pin. The second signal is used to produce a second analog signal. The waveform includes the first signal that is followed by the delineating signal that is followed by the second signal.
摘要翻译：公开了一种用于使用单个微控制器输出引脚来产生多个单独模拟信号的方法和装置。微控制器产生用于同时产生多个分离的模拟信号的波形。微控制器输出包含微控制器输出引脚之一的第一个信号的波形。第一个信号用于产生第一个模拟信号。然后，微控制器从微控制器的输出引脚输出作为波形一部分的描绘信号。描绘信号表示波形中下一个信号的开始。然后，微控制器从其输出引脚输出第二个信号作为波形的一部分。第二信号用于产生第二模拟信号。该波形包括跟随着第二信号的描绘信号后面的第一信号。

4. 发明授权

US07085863B2 I2C device including bus switches and programmable address 有权
标题翻译： I2C器件包括总线开关和可编程地址
公开(公告)号：US07085863B2
公开(公告)日：2006-08-01
申请号：US10698065
申请日：2003-10-30
申请人： Michael Anton Barenys , Stephan Otis Broyles , Robert Allan Faust , Joel Gerard Goodwin
发明人： Michael Anton Barenys , Stephan Otis Broyles , Robert Allan Faust , Joel Gerard Goodwin
IPC分类号： G06F13/00 , G06F11/07
CPC分类号： G06F13/4286
摘要： An I2C device is disclosed that includes a main I2C section, bus switches, switch logic, and address logic as part of the I2C device. The I2C device is coupled to an I2C bus for communicating with other I2C devices and an I2C bus controller that is also on the I2C bus. The switch logic controls a current position of the switches. The I2C device is coupled to the I2C bus utilizing the switches. The switches control whether the main I2C section, the address logic, the switch logic, or a combination of the main I2C section, address logic, and switch logic is currently coupled to I2C bus. The switches also can be used, if desired to remove from the buss all devices that are downstream from a given device containing switches. The address logic is used to receive and store the address of the I2C device. The I2C device will respond to the address that is stored in its address logic.
摘要翻译：公开了一种包括主I 2 C部分，总线开关，开关逻辑和作为I 2 2 C部分的地址逻辑的I < SUP> C设备。 I 2 C装置耦合到I 2 C总线，用于与其他I 2 C装置通信，以及I < / SUP> C总线控制器，也在I ^{2 C总线上。开关逻辑控制开关的当前位置。使用开关将I 2 SUPER C装置耦合到I 2 C总线。开关控制主I 2 S区段，地址逻辑，开关逻辑或主I 2 SUP区段，地址逻辑和开关逻辑的组合目前与I C> C总线相连。如果需要从交换机的给定设备下游的所有设备中删除所有设备，也可以使用交换机。地址逻辑用于接收和存储I ^{2 C设备的地址。 I ^{2 C设备将响应存储在其地址逻辑中的地址。}}}

5. 发明授权

US06769078B2 Method for isolating an I2C bus fault using self bus switching device 失效
标题翻译：使用自总线开关器件隔离I2C总线故障的方法
公开(公告)号：US06769078B2
公开(公告)日：2004-07-27
申请号：US09779368
申请日：2001-02-08
申请人： Michael Anton Barenys , Robert Allan Faust , Joel Gerald Goodwin
发明人： Michael Anton Barenys , Robert Allan Faust , Joel Gerald Goodwin
IPC分类号： G06F1100
CPC分类号： G06F11/221
摘要： A method system, and computer program product for determining the source of a fault within a bus, such as, for example, an inter integrated circuit (I2C) bus is provided. In one embodiment, a bus driver monitors the bus for faults. If a fault occurs on the bus, the bus driver resets each switch on the bus and then turns on the first switch connected to the bus driver. If the fault is encountered after turning on the first switch, then it is determined that the fault was caused by either the first switch, a device connected to the bus as a result of turning on the first switch, or one of the bus connectors just switched on as a result of turning on the first switch. If the fault is not encountered, the next switch is turned on and the process is repeated until the fault is encountered. The fault when encountered will be caused by either the most recently turned on switch or a device or bus connectors switched in by the turning on of the last switch. Thus, the fault can be isolated to a few devices, switches, or bus connections rather than the large number of potential devices, switches, or bus connections that could have potentially caused the fault.
摘要翻译：提供了一种用于确定总线内的故障源（例如，集成电路（I2C）总线）的方法，系统和计算机程序产品。在一个实施例中，总线驱动器监视总线的故障。如果总线上出现故障，总线驱动程序会复位总线上的每个开关，然后打开连接到总线驱动器的第一个开关。如果在打开第一个开关后遇到故障，则确定故障是由第一开关，连接到总线的设备由于打开第一个开关而导致的，或者总线连接器之一作为打开第一个开关的结果打开。如果没有遇到故障，下一个开关打开，重复该过程，直到遇到故障。遇到的故障将由最近打开的开关或通过最后一个开关导通而切换的设备或总线连接器引起。因此，故障可以隔离到几个设备，交换机或总线连接，而不是可能潜在地导致故障的大量潜在设备，交换机或总线连接。

6. 发明申请

US20090037639A1 JTAGCHAIN Bus Switching and Configuring Device 失效
标题翻译： JTAGCHAIN总线切换和配置设备
公开(公告)号：US20090037639A1
公开(公告)日：2009-02-05
申请号：US12251257
申请日：2008-10-14
申请人： Mike Conrad Duron , Robert Allan Faust , Forrest Clifton Gray , Ajay Kumar Mahajan , Glenn Rueban Miles
发明人： Mike Conrad Duron , Robert Allan Faust , Forrest Clifton Gray , Ajay Kumar Mahajan , Glenn Rueban Miles
IPC分类号： G06F13/00
CPC分类号： G01R31/318558 , G01R31/318544 , G01R31/318555 , G06F13/4022
摘要： A JTAG bus cross point switching device that is commanded by the same bus which it configures. In a preferred embodiment a JTAG chain includes a cross point switching device that is capable of adding, omitting, or rearranging devices on a JTAG bus. The switching device itself is controlled by commands on the JTAG bus which it configures.
摘要翻译：一个JTAG总线交叉点交换设备，由其配置的同一总线指令。在优选实施例中，JTAG链包括能够在JTAG总线上添加，省略或重新排列设备的交叉点交换设备。开关设备本身由配置的JTAG总线上的命令控制。

7. 发明授权

US06976197B2 Apparatus and method for error logging on a memory module 失效
标题翻译：记忆模块错误记录的装置和方法
公开(公告)号：US06976197B2
公开(公告)日：2005-12-13
申请号：US09999663
申请日：2001-10-25
申请人： Robert Allan Faust , Joel Gerard Goodwin
发明人： Robert Allan Faust , Joel Gerard Goodwin
IPC分类号： G06F11/10 , G11C29/00
CPC分类号： G06F11/1048 , G11C2029/1208
摘要： An apparatus and method for error logging on a memory module, such as a DIMM, are provided. If an error occurs in a memory module, the operating system of the computing device stores a log of the error in a storage device mounted to the memory module. The log may identify the type and quantity of errors caused by the faulty memory module and may also include defective bit identification information. The defective bit identification information may be used to identify individual memory elements on the memory module that are defective. If the errors exceed a given quality or quantity level, the operating system may store an indicator in the storage device on the memory module that the memory module is defective and take that memory module off-line to prevent problems from occurring with the programs that are running on the computing system.
摘要翻译：提供了用于错误登录在诸如DIMM的存储器模块上的装置和方法。如果内存模块发生错误，则计算设备的操作系统将错误的日志存储在安装到内存模块的存储设备中。日志可以识别由故障存储器模块引起的错误的类型和数量，并且还可以包括有缺陷的位识别信息。有缺陷的位识别信息可用于识别存储器模块中的有缺陷的各个存储元件。如果错误超出给定的质量或数量级别，则操作系统可以将存储器模块中的存储设备中的指示符存储在存储器模块有缺陷的位置，并将该存储器模块脱机，以防止出现与所述程序相关的问题运行在计算系统上。

8. 发明授权

US06725320B1 I2C bus switching devices interspersed between I2C devices 有权
标题翻译： I2C总线交换设备散布在I2C设备之间
公开(公告)号：US06725320B1
公开(公告)日：2004-04-20
申请号：US09779364
申请日：2001-02-08
申请人： Michael Anton Barenys , Robert Allan Faust , Joel Gerald Goodwin
发明人： Michael Anton Barenys , Robert Allan Faust , Joel Gerald Goodwin
IPC分类号： G06F1300
CPC分类号： G06F13/4022
摘要： A bus switch module for use in a bus such as an I2C bus is provided. In one embodiment, the switch module includes a control unit and a switch. The control unit includes an input for receiving instructions from a bus driver as to whether to close or open the switch. The switch includes a first and a second data connection which connect the switch to a first and a second segment of the bus and includes a control input for receiving commands from the control unit. The control unit opens and closes the switch in response to instructions received from the bus driver and signals received in the first data connection are passed to the second data connection only when the switch is closed in response to a command from the control unit.
摘要翻译：提供了一种用于诸如I2C总线的总线的总线开关模块。在一个实施例中，开关模块包括控制单元和开关。控制单元包括用于从总线驱动器接收关于是否关闭或打开开关的指令的输入。开关包括将开关连接到总线的第一和第二段的第一和第二数据连接，并且包括用于从控制单元接收命令的控制输入。控制单元响应于从总线驱动器接收的指令来打开和关闭开关，并且仅当响应于来自控制单元的命令关闭开关时，才将第一数据连接中接收到的信号传递到第二数据连接。

9. 发明授权

US06675293B1 Auxiliary processor manages firmware personalities while borrowing host system resources 失效
标题翻译：辅助处理器在借用主机系统资源的同时管理固件个性
公开(公告)号：US06675293B1
公开(公告)日：2004-01-06
申请号：US09704597
申请日：2000-11-02
申请人： William Eldred Beebe , Christopher L. Canestaro , Robert Allan Faust , Craig Henry Shempert
发明人： William Eldred Beebe , Christopher L. Canestaro , Robert Allan Faust , Craig Henry Shempert
IPC分类号： G06F900
CPC分类号： G06F8/65
摘要： A method and system comprising at least one service processor that is connected to memory and a host system. Additionally, the host system includes at least one host input resource device, such as, for example, a floppy disk, and an interface connecting the host input resource device to the service processor. The interface provides a means for the host input resource device to update, restore, or initialize host system parts or images. In one embodiment, this invention disconnects the host input resource device from main system power and connects it to auxiliary standby power. Thus, the host input resource device makes possible a less costly, less burdensome update of any piece of a data processing system.
摘要翻译：一种方法和系统，包括连接到存储器和主机系统的至少一个服务处理器。此外，主机系统包括至少一个主机输入资源设备，例如软盘，以及将主机输入资源设备连接到服务处理器的接口。该接口提供了主机输入资源设备更新，恢复或初始化主机系统部件或图像的方法。在一个实施例中，本发明将主机输入资源设备与主系统电源断开并将其连接到辅助待机电源。因此，主机输入资源设备使得对于任何数据处理系统的更新成本较低，成本更低。

10. 发明授权

US06334165B1 Address type determination for an I2C EEPROM 失效
公开(公告)号：US06334165B1
公开(公告)日：2001-12-25
申请号：US09436107
申请日：1999-11-08
申请人： Michael Anton Barenys , William Eldred Beebe , Robert Allan Faust , Joel G. Goodwin
发明人： Michael Anton Barenys , William Eldred Beebe , Robert Allan Faust , Joel G. Goodwin
IPC分类号： G06F1200
CPC分类号： G06F12/0684 , G11C16/08 , G11C2216/30
摘要： A method, system, and computer program product are disclosed for determining the address type of a serial EEPROM in an electronic system. The method includes reading data from at least one location of the EEPROM for a first time and saving the data for future reference. Thereafter, a sequence of transactions is executed that alters the contents of the EEPROM in a prescribed manner if the EEPROM is of a first type. The sequence of transaction leaves the EEPROM in an unaltered state if the EEPROM is of a second type. Data is then read from at least one location of the EEPROM for a second time. The location of the data read from the EEPROM the second time is the same as the location of the data read the first time if the EEPROM is of the first type. The data read the first time and the data read the second time are then compared. If it is determined that the data read the second time does not differ in the prescribed manner from the data read the first time, the type of the EEPROM is identified as the second type. In one embodiment, the indicate steps are repeated to achieve additional assurance that type of the EEPROM is the first type if it is determined that the data read the second time differs in the prescribed manner from the data read the first time. In one embodiment, reading data from the EEPROM for the first time includes, writing an initial byte to the EEPROM for a first time to set the address pointer to a known state if the EEPROM is of the first type. In one embodiment, the sequence of transactions include writing two bytes to the EEPROM, wherein the value of the first of the two bytes is the value of the initial byte written to the EEPROM. In one embodiment, the method includes, prior to reading data from the EEPROM for the first time writing two bytes to the EEPROM if is determined that the EEPROM is configured with an address type indicator field, where the two bytes comprise the 2-byte address of the indicator field in an EEPROM of the second type. In this embodiment, the two bytes of address type indicator information are read from the EEPROM. The contents of the two bytes are indicative of the address type of the EEPROM.

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