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1. 发明申请

US20120223317A1 OHMIC CONTACT SCHEMES FOR GROUP III-V DEVICES HAVING A TWO-DIMENSIONAL ELECTRON GAS LAYER 有权
标题翻译：具有二维电子气体层的III-V族设备的OHMIC接触方案
公开(公告)号：US20120223317A1
公开(公告)日：2012-09-06
申请号：US13037974
申请日：2011-03-01
申请人： Sandeep R. Bahl , Richard W. Foote, JR.
发明人： Sandeep R. Bahl , Richard W. Foote, JR.
IPC分类号： H01L29/20 , H01L21/28
CPC分类号： H01L29/7787 , H01L21/28587 , H01L29/2003 , H01L29/4175 , H01L29/41758 , H01L29/41766 , H01L29/66462
摘要： A semiconductor device includes a first layer and a second layer over the first layer. The first and second layers are configured to form an electron gas layer at an interface of the first and second layers. The semiconductor device also includes an Ohmic contact and multiple conductive vias through the second layer. The conductive vias are configured to electrically couple the Ohmic contact to the electron gas layer. The conductive vias could have substantially vertical sidewalls or substantially sloped sidewalls, or the conductive vias could form a nano-textured surface on the Ohmic contact. The first layer could include Group III-nitride nucleation, buffer, and channel layers, and the second layer could include a Group III-nitride barrier layer.
摘要翻译：半导体器件包括在第一层上的第一层和第二层。第一层和第二层被配置为在第一层和第二层的界面处形成电子气层。半导体器件还包括通过第二层的欧姆接触和多个导电通孔。导电通孔被配置为将欧姆接触电耦合到电子气体层。导电通孔可以具有基本上垂直的侧壁或基本上倾斜的侧壁，或者导电通孔可以在欧姆接触件上形成纳米纹理表面。第一层可以包括III族氮化物成核，缓冲层和沟道层，第二层可以包括III族氮化物阻挡层。

2. 发明授权

US07863153B1 System and method for creating different field oxide profiles in a locos process 有权
标题翻译：在定位过程中创建不同场氧化物剖面的系统和方法
公开(公告)号：US07863153B1
公开(公告)日：2011-01-04
申请号：US11486987
申请日：2006-07-13
申请人： Richard W. Foote, Jr.
发明人： Richard W. Foote, Jr.
IPC分类号： H01L21/76
CPC分类号： H01L21/76202 , Y10S438/981
摘要： An efficient method is disclosed for creating different field oxide profiles in a local oxidation of silicon process (LOCOS process). The method comprises (1) forming a first portion of the field oxide with a first field oxide profile (e.g., an abrupt bird's beak profile) during a field oxide oxidation process, and (2) forming a second portion of the field oxide with a second field oxide profile (e.g., a graded bird's beak profile) during the field oxide oxidation process. A graded bird's beak profile enables higher breakdown voltages. An abrupt bird's beak profile enables higher packing densities. The method gives an integrated circuit designer the flexibility to create an appropriate field oxide profile at a desired location.
摘要翻译：公开了一种用于在硅工艺的局部氧化（LOCOS工艺）中产生不同的场氧化物分布的有效方法。该方法包括：（1）在场氧化物氧化过程期间，形成场氧化物的第一部分，其具有第一场氧化物分布（例如，突然的鸟的喙轮廓），和（2）用场氧化物形成第二部分的氧化物在场氧化物氧化过程中的第二场氧化物轮廓（例如，分级鸟的喙轮廓）。分级鸟的喙廓可以提供更高的击穿电压。突然的鸟嘴形状使得更高的包装密度。该方法给集成电路设计者在所需位置创建适当的场氧化物分布的灵活性。

3. 发明授权

US08946780B2 Ohmic contact schemes for group III-V devices having a two-dimensional electron gas layer 有权
标题翻译：具有二维电子气体层的III-V族元件的欧姆接触方案
公开(公告)号：US08946780B2
公开(公告)日：2015-02-03
申请号：US13037974
申请日：2011-03-01
申请人： Sandeep R. Bahl , Richard W. Foote, Jr.
发明人： Sandeep R. Bahl , Richard W. Foote, Jr.
IPC分类号： H01L21/285 , H01L21/02 , H01L29/45 , H01L29/778 , H01L29/417 , H01L29/66 , H01L29/20
CPC分类号： H01L29/7787 , H01L21/28587 , H01L29/2003 , H01L29/4175 , H01L29/41758 , H01L29/41766 , H01L29/66462
摘要： A semiconductor device includes a first layer and a second layer over the first layer. The first and second layers are configured to form an electron gas layer at an interface of the first and second layers. The semiconductor device also includes an Ohmic contact and multiple conductive vias through the second layer. The conductive vias are configured to electrically couple the Ohmic contact to the electron gas layer. The conductive vias could have substantially vertical sidewalls or substantially sloped sidewalls, or the conductive vias could form a nano-textured surface on the Ohmic contact. The first layer could include Group III-nitride nucleation, buffer, and channel layers, and the second layer could include a Group III-nitride barrier layer.
摘要翻译：半导体器件包括在第一层上的第一层和第二层。第一层和第二层被配置为在第一层和第二层的界面处形成电子气层。半导体器件还包括通过第二层的欧姆接触和多个导电通孔。导电通孔被配置为将欧姆接触电耦合到电子气体层。导电通孔可以具有基本上垂直的侧壁或基本上倾斜的侧壁，或者导电通孔可以在欧姆接触件上形成纳米纹理表面。第一层可以包括III族氮化物成核，缓冲层和沟道层，第二层可以包括III族氮化物阻挡层。

4. 发明授权

US07456097B1 System and method for faceting via top corners to improve metal fill 有权
标题翻译：通过顶角进行刻面的系统和方法，以改善金属填充
公开(公告)号：US07456097B1
公开(公告)日：2008-11-25
申请号：US10999542
申请日：2004-11-30
申请人： Rodney Hill , Victor M. Torres , Richard W. Foote, Jr.
发明人： Rodney Hill , Victor M. Torres , Richard W. Foote, Jr.
IPC分类号： H01L21/4763
CPC分类号： H01L21/76804
摘要： A system and method is disclosed for providing an etch procedure to facet the top corners of a via in a semiconductor device. A vertical anisotropic dry etch process is applied through an aperture in a resist mask to etch through a dielectric layer down to a bottom conductor layer. The resist mask is removed and an etch process is applied to etch away corner portions of the dielectric layer. The etch process forms a flat sidewall surface in the portions of the dielectric layer that form the via. The flat sidewall surface is disposed at an obtuse angle with respect to the top surface of the dielectric layer and at an obtuse angle with respect to a vertical sidewall of the via cavity. The flat sidewall surface and the absence of sharp corners facilitate a subsequent metal fill process.
摘要翻译：公开了一种用于提供蚀刻过程以在半导体器件中刻面通孔的顶角的系统和方法。通过抗蚀剂掩模中的孔施加垂直各向异性干蚀刻工艺，以通过介电层蚀刻到底部导体层。去除抗蚀剂掩模并施加蚀刻工艺以蚀刻掉电介质层的角部。蚀刻工艺在形成通孔的介电层的部分中形成平坦的侧壁表面。扁平侧壁表面相对于电介质层的顶表面以钝角设置，并且相对于通孔腔的垂直侧壁以钝角设置。平坦的侧壁表面和没有锋利的拐角有助于随后的金属填充过程。

5. 发明授权

US07332403B1 System and method for providing a buried thin film resistor having end caps defined by a dielectric mask 有权
标题翻译：用于提供具有由介电掩模限定的端盖的掩埋薄膜电阻器的系统和方法
公开(公告)号：US07332403B1
公开(公告)日：2008-02-19
申请号：US11179022
申请日：2005-07-11
申请人： Rodney Hill , Victor Torres , William Max Coppock , Richard W. Foote, Jr. , Terry L. Lines , Tom Bold
发明人： Rodney Hill , Victor Torres , William Max Coppock , Richard W. Foote, Jr. , Terry L. Lines , Tom Bold
IPC分类号： H01L21/20
CPC分类号： H01L28/20
摘要： A buried thin film resistor having end caps defined by a dielectric mask is disclosed. A thin film resistor is formed on an integrated circuit substrate. A resistor protect layer is formed over the thin film resistor. A layer of dielectric material is formed over the resistor protect layer. The dielectric material is masked and dry etched to leave a first portion of dielectric material over a first end of the thin film resistor and a second portion of dielectric material over a second end of the thin film resistor. The resistor protect layer is then wet etched using the first and second portions of the dielectric material as a hard mask. Then a second dielectric layer is deposited and vias are etched down to the underlying portions of the resistor protect layer.
摘要翻译：公开了一种具有由介电掩模限定的端盖的掩埋薄膜电阻器。在集成电路基板上形成薄膜电阻。在薄膜电阻上形成电阻保护层。电介质材料层形成在电阻器保护层上。电介质材料被掩蔽和干蚀刻以在薄膜电阻器的第一端上方留下电介质材料的第一部分，并且在薄膜电阻器的第二端上延伸第二部分电介质材料。然后使用电介质材料的第一和第二部分作为硬掩模来湿式蚀刻电阻器保护层。然后沉积第二电介质层，并将通孔蚀刻到电阻器保护层的下面部分。

6. 发明申请

US20110065256A1 SYSTEM AND METHOD FOR INCREASING BREAKDOWN VOLTAGE OF LOCOS ISOLATED DEVICES 审中-公开
标题翻译：用于增加LOCOS隔离装置的突然电压的系统和方法
公开(公告)号：US20110065256A1
公开(公告)日：2011-03-17
申请号：US12955194
申请日：2010-11-29
申请人： Richard W. Foote, JR. , Terry Lee Lines , Alexei Sadovnikov , Andy Strachan
发明人： Richard W. Foote, JR. , Terry Lee Lines , Alexei Sadovnikov , Andy Strachan
IPC分类号： H01L21/762
CPC分类号： H01L21/76205
摘要： An efficient method is disclosed for increasing the breakdown voltage of an integrated circuit device that is isolated by a local oxidation of silicon (LOCOS) process. The method comprises forming a portion of a field oxide in an integrated circuit so that the field oxide has a gradual profile. The gradual profile of the field oxide reduces impact ionization in the field oxide by creating a reduced value of electric field for a given value of applied voltage. The reduction in impact ionization increases the breakdown voltage of the integrated circuit. The gradual profile is formed by using an increased thickness of pad oxide and a reduced thickness of silicon nitride during a field oxide oxidation process.
摘要翻译：公开了一种有效的方法来增加由硅（LOCOS）工艺的局部氧化隔离的集成电路器件的击穿电压。该方法包括在集成电路中形成场氧化物的一部分，使得场氧化物具有逐渐的轮廓。场氧化物的逐渐轮廓通过为给定的施加电压值产生减小的电场值来减少场氧化物中的冲击电离。冲击电离的减少增加了集成电路的击穿电压。通过在场氧化物氧化过程中通过使用增加的衬垫氧化物的厚度和减小的氮化硅的厚度来形成渐变曲线。

7. 发明授权

US07808048B1 System and method for providing a buried thin film resistor having end caps defined by a dielectric mask 有权
标题翻译：用于提供具有由介电掩模限定的端盖的掩埋薄膜电阻器的系统和方法
公开(公告)号：US07808048B1
公开(公告)日：2010-10-05
申请号：US11974647
申请日：2007-10-15
申请人： Rodney Hill , Victor Torres , William Max Coppock , Richard W. Foote, Jr. , Terry L. Lines , Tom Bold
发明人： Rodney Hill , Victor Torres , William Max Coppock , Richard W. Foote, Jr. , Terry L. Lines , Tom Bold
IPC分类号： H01L23/62
CPC分类号： H01L28/20
摘要： A buried thin film resistor having end caps defined by a dielectric mask is disclosed. A thin film resistor is formed on an integrated circuit substrate. A resistor protect layer is formed over the thin film resistor. A layer of dielectric material is formed over the resistor protect layer. The dielectric material is masked and dry etched to leave a first portion of dielectric material over a first end of the thin film resistor and a second portion of dielectric material over a second end of the thin film resistor. The resistor protect layer is then wet etched using the first and second portions of the dielectric material as a hard mask. Then a second dielectric layer is deposited and vias are etched down to the underlying portions of the resistor protect layer.
摘要翻译：公开了一种具有由介电掩模限定的端盖的掩埋薄膜电阻器。在集成电路基板上形成薄膜电阻。在薄膜电阻上形成电阻保护层。电介质材料层形成在电阻器保护层上。电介质材料被掩蔽和干蚀刻以在薄膜电阻器的第一端上方留下电介质材料的第一部分，并且在薄膜电阻器的第二端上延伸第二部分电介质材料。然后使用电介质材料的第一和第二部分作为硬掩模来湿式蚀刻电阻器保护层。然后沉积第二介电层，并将通孔蚀刻到电阻器保护层的下面部分。

8. 发明授权

US07470594B1 System and method for controlling the formation of an interfacial oxide layer in a polysilicon emitter transistor 有权
标题翻译：用于控制多晶硅发射极晶体管中界面氧化物层形成的系统和方法
公开(公告)号：US07470594B1
公开(公告)日：2008-12-30
申请号：US11302920
申请日：2005-12-14
申请人： Richard W. Foote, Jr. , William Max Coppock , Darren Lee Rust , Charles A. Dark
发明人： Richard W. Foote, Jr. , William Max Coppock , Darren Lee Rust , Charles A. Dark
IPC分类号： H01L21/331 , H01L21/8222
CPC分类号： H01L21/31662 , H01L21/02238 , H01L21/02255 , H01L29/0804 , Y10S438/905
摘要： A method is disclosed for controlling the formation of an interfacial oxide layer in a polysilicon emitter transistor device. The interfacial oxide layer is formed between an underlying substrate of single crystal silicon and an upper layer of polysilicon. The current gain and the emitter resistance of the transistor device are related to the thickness of the interfacial oxide layer. The oxide of the interfacial oxide layer is grown in a low pressure, low temperature pure oxygen (O2) environment that greatly reduces the oxidation rate. The low oxidation rate allows the thickness of the interfacial oxide layer to be precisely controlled and sources of variation to be minimized in the manufacturing process.
摘要翻译：公开了一种用于控制多晶硅发射极晶体管器件中的界面氧化物层的形成的方法。界面氧化物层形成在单晶硅的下面的衬底和多晶硅的上层之间。晶体管器件的电流增益和发射极电阻与界面氧化物层的厚度有关。界面氧化物层的氧化物在低压，低温纯氧（O 2）环境中生长，大大降低了氧化速率。低氧化速率允许在制造过程中精细控制界面氧化物层的厚度和变化的来源。

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