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1. 发明申请

US20090183130A1 System and Method for Improved Hierarchical Analysis of Electronic Circuits 有权
标题翻译：改进电子电路分层分析的系统与方法
公开(公告)号：US20090183130A1
公开(公告)日：2009-07-16
申请号：US11972923
申请日：2008-01-11
申请人： Philip G. Shephard, III , Ravichander Ledalla , Vasant Rao , Jeffrey P. Soreff
发明人： Philip G. Shephard, III , Ravichander Ledalla , Vasant Rao , Jeffrey P. Soreff
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method for hierarchical analysis of electronic circuits comprises selecting a first one of a plurality of abstraction levels of a general design model (GDM). The GDM comprises a first design description of electronic circuits at a plurality of abstraction levels and a plurality of foci, organized into sub-blocks. The method selects a first focus of the plurality of foci to select a first sub-block. The method identifies incomplete electronic circuits in the selected first sub-block. The method generates a second design description of the first sub-block to exclude identified incomplete electronic circuits, wherein the second design description is suitable for electronic design analysis (EDA). The method stores the generated second design description for subsequent use. Subsequent iterations thereby include all components of circuits that were incomplete in prior iterations.
摘要翻译：一种用于电子电路的层次分析的方法包括选择通用设计模型（GDM）的多个抽象层中的第一个抽象层。 GDM包括在多个抽象级别的电子电路的第一设计描述和被组织成子块的多个焦点。该方法选择多个焦点的第一焦点以选择第一子块。该方法识别所选择的第一子块中不完整的电子电路。该方法产生第一子块的第二设计描述以排除所识别的不完整电子电路，其中第二设计描述适用于电子设计分析（EDA）。该方法存储生成的第二设计描述供后续使用。随后的迭代因此包括在先前迭代中不完整的电路的所有组件。

2. 发明授权

US08201120B2 Timing point selection for a static timing analysis in the presence of interconnect electrical elements 有权
标题翻译：在存在互连电气元件的情况下进行静态时序分析的时序点选择
公开(公告)号：US08201120B2
公开(公告)日：2012-06-12
申请号：US12652338
申请日：2010-01-05
申请人： Jeffrey P. Soreff , Barry Lee Dorfman , Jeffrey G. Hemmett , Ravichander Ledalla , Vasant Rao , Fred Lei Yang
发明人： Jeffrey P. Soreff , Barry Lee Dorfman , Jeffrey G. Hemmett , Ravichander Ledalla , Vasant Rao , Fred Lei Yang
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5031
摘要： A method and a system for selecting timing points in an electrical interconnect network to be used in electrical simulations for a static timing analysis for improved accuracy. The present method includes discovering choke points in an electrical model of the interconnect for which all the paths from drivers to receivers must pass through on certain types of nets. The method then uses the choke point electrical nodes, where they exist, as an output timing point of the logic gate driving the net. The method solves the problem of inaccuracies due to resistances between different driver pins on the same interconnect net, though it can also be applied to solving analogous inaccuracies due to resistances between different receiver pins associated with the same receiver timing point. It further also applies to interconnect with other two-port parasitic elements, to cases where only a subset of receiver pins on the net require accurate timing, and to cases where a set of electrical nodes, rather than a single node, partition all paths from drivers to receivers on a net.
摘要翻译：一种用于选择电气互连网络中用于静态时序分析的电气仿真中的定时点的方法和系统，以提高精度。本发明的方法包括发现在互连的电气模型中的阻塞点，所述互连的所有路径对于所述路由器必须在某些类型的网络上通过。然后，该方法使用其存在的阻塞点电子节点作为驱动网络的逻辑门的输出定时点。该方法解决了由于同一互连网上的不同驱动器引脚之间的电阻引起的不准确性的问题，尽管它也可以应用于解决由于与相同接收器定时点相关联的不同接收器引脚之间的电阻引起的类似不准确性。它还适用于与其他双端口寄生元件的互连，仅在网络上的接收器引脚的子集需要精确的定时的情况下，以及一组电气节点而不是单个节点将所有路径从驱动程序到网络上的接收器。

3. 发明授权

US07870515B2 System and method for improved hierarchical analysis of electronic circuits 有权
标题翻译：改进电子电路层次分析的系统和方法
公开(公告)号：US07870515B2
公开(公告)日：2011-01-11
申请号：US11972923
申请日：2008-01-11
申请人： Philip G. Shephard, III , Ravichander Ledalla , Vasant Rao , Jeffrey P. Soreff
发明人： Philip G. Shephard, III , Ravichander Ledalla , Vasant Rao , Jeffrey P. Soreff
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method for hierarchical analysis of electronic circuits comprises selecting a first one of a plurality of abstraction levels of a general design model (GDM). The GDM comprises a first design description of electronic circuits at a plurality of abstraction levels and a plurality of foci, organized into sub-blocks. The method selects a first focus of the plurality of foci to select a first sub-block. The method identifies incomplete electronic circuits in the selected first sub-block. The method generates a second design description of the first sub-block to exclude identified incomplete electronic circuits, wherein the second design description is suitable for electronic design analysis (EDA). The method stores the generated second design description for subsequent use. Subsequent iterations thereby include all components of circuits that were incomplete in prior iterations.
摘要翻译：一种用于电子电路的层次分析的方法包括选择通用设计模型（GDM）的多个抽象层中的第一个抽象层。 GDM包括在多个抽象级别的电子电路的第一设计描述和被组织成子块的多个焦点。该方法选择多个焦点的第一焦点以选择第一子块。该方法识别所选择的第一子块中不完整的电子电路。该方法产生第一子块的第二设计描述以排除所识别的不完整电子电路，其中第二设计描述适用于电子设计分析（EDA）。该方法存储生成的第二设计描述供后续使用。随后的迭代因此包括在先前迭代中不完整的电路的所有组件。

4. 发明申请

US20110167395A1 Timing Point Selection For A Static Timing Analysis In The Presence Of Interconnect Electrical Elements 有权
标题翻译：在互连电气元件存在下的静态时序分析的时序点选择
公开(公告)号：US20110167395A1
公开(公告)日：2011-07-07
申请号：US12652338
申请日：2010-01-05
申请人： Jeffrey P. Soreff , Barry Lee Dorfman , Jeffrey G. Hemmett , Ravichander Ledalla , Vasant Rao , Fred Lei Yang
发明人： Jeffrey P. Soreff , Barry Lee Dorfman , Jeffrey G. Hemmett , Ravichander Ledalla , Vasant Rao , Fred Lei Yang
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method and a system for selecting timing points in an electrical interconnect network to be used in electrical simulations for a static timing analysis for improved accuracy. The present method includes discovering choke points in an electrical model of the interconnect for which all the paths from drivers to receivers must pass through on certain types of nets. The method then uses the choke point electrical nodes, where they exist, as an output timing point of the logic gate driving the net. The method solves the problem of inaccuracies due to resistances between different driver pins on the same interconnect net, though it can also be applied to solving analogous inaccuracies due to resistances between different receiver pins associated with the same receiver timing point. It further also applies to interconnect with other two-port parasitic elements, to cases where only a subset of receiver pins on the net require accurate timing, and to cases where a set of electrical nodes, rather than a single node, partition all paths from drivers to receivers on a net.
摘要翻译：一种用于选择电气互连网络中用于静态时序分析的电气仿真中的定时点的方法和系统，以提高精度。本发明的方法包括发现在互连的电气模型中的阻塞点，所述互连的所有路径对于所述路由器必须在某些类型的网络上通过。然后，该方法使用其存在的阻塞点电子节点作为驱动网络的逻辑门的输出定时点。该方法解决了由于同一互连网上的不同驱动器引脚之间的电阻引起的不准确性的问题，尽管它也可以用于解决由于与相同接收器定时点相关联的不同接收器引脚之间的电阻引起的类似不准确性。它还适用于与其他双端口寄生元件的互连，仅在网络上的接收器引脚的子集需要精确的定时的情况下，以及一组电气节点而不是单个节点将所有路径从驱动程序到网络上的接收器。

5. 发明授权

US06763504B2 Method for reducing RC parasitics in interconnect networks of an integrated circuit 失效
标题翻译：降低集成电路互连网络中RC寄生效应的方法
公开(公告)号：US06763504B2
公开(公告)日：2004-07-13
申请号：US10237328
申请日：2002-09-06
申请人： Vasant B. Rao , Ravichander Ledalla , Jeffrey P. Soreff , Fred L. Yang
发明人： Vasant B. Rao , Ravichander Ledalla , Jeffrey P. Soreff , Fred L. Yang
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： A method for further reducing RC parasitics in an interconnect network following internal node elimination is described. A resistor is initially selected as a candidate for shorting, and it is established whether the accumulated delay error at either end of the resistor is less than a predetermined threshold. This threshold must be a fraction of the time-constant threshold selected by internal node elimination techniques in order to limit the growth of the accumulated delay errors. An important aspect of the invention is the simplicity of the formula used to change the downstream resistor values, namely, the product of the value of the resistor shorted and the ratio of the cumulative downstream capacitances of the two ends of the resistor whose value is being changed. This particular choice of updating the downstream resistor values minimizes the absolute-value of the delay errors at every node due to shorting of the selected resistor. It also preserves the delays at all nodes in the interconnect network apart from the two ends of the resistor selected for shorting.
摘要翻译：描述了在内部节点消除之后进一步减少互连网络中的RC寄生效应的方法。最初选择一个电阻作为短路的候选，并且确定电阻器两端的累积延迟误差是否小于预定阈值。该阈值必须是通过内部节点消除技术选择的时间常数阈值的一小部分，以便限制累积延迟误差的增长。本发明的一个重要方面是用于改变下游电阻值的公式的简单性，即，电阻器的值的乘积与电阻器的两端的累积下游电容的比值，其值为改变了更新下游电阻值的这一特定选择可以使由于所选择的电阻器的短路导致的每个节点的延迟误差的绝对值最小化。它还保留互连网络中所有节点之间的延迟，除了选择短路的电阻器的两端之外。

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