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1. 发明申请

US20120112776A1 THREE-DIMENSIONAL (3D) STACKED INTEGRATED CIRCUIT TESTING 有权
标题翻译：三维（3D）堆叠集成电路测试
公开(公告)号：US20120112776A1
公开(公告)日：2012-05-10
申请号：US12942662
申请日：2010-11-09
申请人： Chen-Yong Cher , Eren Kursun , Gary W. Maier , Raphael P. Robertazzi
发明人： Chen-Yong Cher , Eren Kursun , Gary W. Maier , Raphael P. Robertazzi
IPC分类号： G01R31/10
CPC分类号： G01R31/2817 , G01R31/287
摘要： Testing of a three-dimensional (3D) integrated circuit includes defining a first group of parts by a region and/or layer on the 3D integrated circuit. The testing further includes applying a first intensity of stress test conditions to the first group of parts. The testing also includes defining a second group of parts by a region and/or layer on the 3D integrated circuit that is different from the first group of parts. The testing further includes and applying a second intensity of stress test conditions to the second group of parts. The second intensity of stress test conditions is greater than the first intensity and is determined by sensitivities identified for each of the first and second group of parts. A determination is made whether the 3D integrated circuit passed the testing based upon results of application of the first and second intensities of stress test conditions.
摘要翻译：三维（3D）集成电路的测试包括通过3D集成电路上的区域和/或层定义第一组部分。测试还包括将第一强度的应力测试条件应用于第一组零件。测试还包括通过与第一组部件不同的3D集成电路上的区域和/或层定义第二组部件。测试进一步包括并将第二强度的应力测试条件应用于第二组零件。应力测试条件的第二强度大于第一强度，并且由针对第一组和第二组部件确定的灵敏度确定。根据第一和第二强度应力测试条件的应用结果，确定3D集成电路是否通过了测试。

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