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1. 发明授权

US06199057B1 Bit-serial neuroprocessor architecture 失效
标题翻译：位串行神经处理器架构
公开(公告)号：US06199057B1
公开(公告)日：2001-03-06
申请号：US08956890
申请日：1997-10-23
申请人： Raoul Tawel
发明人： Raoul Tawel
IPC分类号： G06F1518
CPC分类号： G01M15/11
摘要： A neuroprocessor architecture employs a combination of bit-serial and serial-parallel techniques for implementing the neurons of the neuroprocessor. The neuroprocessor architecture includes a neural module containing a pool of neurons, a global controller, a sigmoid activation ROM look-up-table, a plurality of neuron state registers, and a synaptic weight RAM. The neuroprocessor reduces the number of neurons required to perform the task by time multiplexing groups of neurons from a fixed pool of neurons to achieve the successive hidden layers of a recurrent network topology.
摘要翻译：神经处理器架构采用位串行和串行并行技术的组合来实现神经处理器的神经元。神经处理器架构包括包含神经元池的神经模块，全局控制器，S形激活ROM查找表，多个神经元状态寄存器和突触权重RAM。神经处理器通过从固定的神经元池中时间复用神经元组来减少执行任务所需的神经元数量，以实现复现网络拓扑的连续隐藏层。

2. 发明授权

US06434541B1 Automotive engine misfire detection system including a bit-serial based recurrent neuroprocessor 失效
标题翻译：汽车发动机失火检测系统包括基于位串的反复式神经处理器
公开(公告)号：US06434541B1
公开(公告)日：2002-08-13
申请号：US09284843
申请日：1999-04-21
申请人： Raoul Tawel , Nazeeh Aranki , Lee A. Feldkamp , Gintaras V. Puskorius , Kenneth A. Marko , John V. James
发明人： Raoul Tawel , Nazeeh Aranki , Lee A. Feldkamp , Gintaras V. Puskorius , Kenneth A. Marko , John V. James
IPC分类号： G06F1518
CPC分类号： G01M15/11
摘要： An engine diagnostic system includes a bit-serial based recurrent neuroprocessor for processing data from an internal combustion engine in order to diagnose misfires in real-time and reduces the number of neurons required to perform the task by time multiplexing groups of neurons from a candidate pool of neurons to achieve the successive hidden layers of the recurrent network topology.
摘要翻译：发动机诊断系统包括用于处理来自内燃机的数据的基于位串的反复式神经处理器，以便实时地诊断失火，并且通过从候选池时间复用神经元组来减少执行任务所需的神经元数量的神经元来实现复发网络拓扑的连续隐藏层。

3. 发明授权

US5506801A High-performance ultra-low power VLSI analog processor for data compression 失效
标题翻译：用于数据压缩的高性能超低功耗VLSI模拟处理器
公开(公告)号：US5506801A
公开(公告)日：1996-04-09
申请号：US196295
申请日：1994-02-14
申请人： Raoul Tawel
发明人： Raoul Tawel
IPC分类号： G06T9/00 , H03M7/30 , G06G7/00
CPC分类号： G06T9/008 , H03M7/3082
摘要： An apparatus for data compression employing a parallel analog processor. The apparatus includes an array of processor cells with N columns and M rows wherein the processor cells have an input device, memory device, and processor device. The input device is used for inputting a series of input vectors. Each input vector is simultaneously input into each column of the array of processor cells in a pre-determined sequential order. An input vector is made up of M components, ones of which are input into ones of M processor cells making up a column of the array. The memory device is used for providing ones of M components of a codebook vector to ones of the processor cells making up a column of the array. A different codebook vector is provided to each of the N columns of the array. The processor device is used for simultaneously comparing the components of each input vector to corresponding components of each codebook vector, and for outputting a signal representative of the closeness between the compared vector components. A combination device is used to combine the signal output from each processor cell in each column of the array and to output a combined signal. A closeness determination device is then used for determining which codebook vector is closest to an input vector from the combined signals, and for outputting a codebook vector index indicating which of the N codebook vectors was the closest to each input vector input into the array.
摘要翻译：一种采用并行模拟处理器的数据压缩装置。该装置包括具有N列和M行的处理器单元的阵列，其中处理器单元具有输入装置，存储装置和处理器装置。输入设备用于输入一系列输入向量。每个输入向量以预定的顺序顺序同时输入到处理器单元阵列的每一列。输入向量由M个分量组成，其中一个分量被输入到构成数组列的M个处理器单元中。存储器件用于将码本矢量的M个分量中的一个组成一个组成阵列列的处理器单元。向阵列的N列中的每一列提供不同的码本向量。处理器装置用于将每个输入向量的分量与每个码本向量的相应分量进行比较，并用于输出表示比较矢量分量之间的接近度的信号。组合装置用于组合阵列每列中每个处理器单元的信号输出并输出组合信号。然后使用接近度确定装置来确定哪个码本向量与组合信号最接近于输入向量，并且用于输出指示N个码本向量中哪一个最接近输入到阵列中的每个输入向量的码本向量索引。

4. 发明授权

US5371834A Adaptive neuron model--an architecture for the rapid learning of nonlinear topological transformations 失效
标题翻译：自适应神经元模型 - 用于非线性拓扑变换的快速学习的架构
公开(公告)号：US5371834A
公开(公告)日：1994-12-06
申请号：US937335
申请日：1992-08-28
申请人： Raoul Tawel
发明人： Raoul Tawel
IPC分类号： B25J9/16 , G06N3/04 , G06F15/18
CPC分类号： G06K9/6251 , B25J9/1607 , G06N3/0445 , G05B2219/39271
摘要： A method and an apparatus for the rapid learning of nonlinear mappings and topological transformations using a dynamically reconfigurable artificial neural network is presented. This fully-recurrent Adaptive Neuron Model (ANM) network has been applied to the highly degenerative inverse kinematics problem in robotics, and its performance evaluation is bench-marked. Once trained, the resulting neuromorphic architecture was implemented in custom analog neural network hardware and the parameters capturing the functional transformation downloaded onto the system. This neuroprocessor, capable of 10.sup.9 ops/sec, was interfaced directly to a three degree of freedom Heathkit robotic manipulator. Calculation of the hardware feed-forward pass for this mapping was benchmarked at .apprxeq.10 .mu.sec.
摘要翻译：提出了使用动态可重构的人工神经网络快速学习非线性映射和拓扑变换的方法和装置。这种完全复现的自适应神经元模型（ANM）网络已经应用于机器人技术中的高度退化的逆运动学问题，其性能评估被标准化。一旦训练，所得到的神经元结构在定制的模拟神经网络硬件中实现，并且参数捕获功能转换下载到系统上。这种具有109次操作/秒的神经处理器直接连接到三自由度Heathkit机器人操纵器。该映射的硬件前馈通过计算以APPROX 10微秒为基准。

5. 发明授权

US5299285A Neural network with dynamically adaptable neurons 失效
标题翻译：具有动态适应神经元的神经网络
公开(公告)号：US5299285A
公开(公告)日：1994-03-29
申请号：US071206
申请日：1993-05-27
申请人： Raoul Tawel
发明人： Raoul Tawel
IPC分类号： G06N3/063 , G06F15/18 , G06G7/19
CPC分类号： G06N3/0635
摘要： This invention is an adaptive neuron for use in neural network processors. The adaptive neuron participates in the supervised learning phase of operation on a coequal basis with the synapse matrix elements by adaptively changing its gain in a similar manner to the change of weights in the synapse io elements. In this manner, training time is decreased by as much as three orders of magnitude.
摘要翻译：本发明是用于神经网络处理器的自适应神经元。自适应神经元通过以与突触io元素中的权重变化相似的方式自适应地改变其增益，参与与突触矩阵元素相等的操作的监督学习阶段。以这种方式，训练时间减少了三个数量级。

6. 发明授权

US5298796A Nonvolatile programmable neural network synaptic array 失效
标题翻译：非易失性可编程神经网络突触阵列
公开(公告)号：US5298796A
公开(公告)日：1994-03-29
申请号：US912956
申请日：1992-07-08
申请人： Raoul Tawel
发明人： Raoul Tawel
IPC分类号： G06N3/063 , H03K19/08
CPC分类号： G06N3/063 , G06N3/0635
摘要： A floating-gate MOS transistor is implemented for use as a nonvolatile analog storage element of a synaptic cell used to implement an array of processing synaptic cells based on a four-quadrant analog multiplier requiring both X and Y differential inputs, where one Y input is UV programmable. These nonvolatile synaptic cells are disclosed fully connected in a 32.times.32 synaptic cell array using standard VLSI CMOS technology.
摘要翻译：实施浮栅MOS晶体管用作突触单元的非易失性模拟存储元件，用于基于需要X和Y差分输入的四象限模拟乘法器来实现处理突触单元阵列，其中一个Y输入为 UV可编程。这些非易失性突触细胞被公开使用标准VLSI CMOS技术完全连接在32 * 32突触细胞阵列中。

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