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1. 发明授权

US09128849B2 Coherent memory scheme for heterogeneous processors 有权
标题翻译：用于异构处理器的相干存储器方案
公开(公告)号：US09128849B2
公开(公告)日：2015-09-08
申请号：US13082139
申请日：2011-04-07
申请人： Ian Hendry , Rajabali Koduri
发明人： Ian Hendry , Rajabali Koduri
IPC分类号： G06F12/08 , G06F12/02 , G06F12/10
CPC分类号： G06F12/0835 , G06F12/0831 , G06F12/1045
摘要： Systems, methods, and devices for maintaining cache coherence between two or more heterogeneous processors are provided. In accordance with one embodiment, such an electronic device may include memory, a first processing unit having a first characteristic memory usage rate, and a second processing unit having a second characteristic memory usage rate lower than the first. The first and second processing units may share at least a portion of the memory and one or both of the first and second processing units may maintain internal cache coherence at a first granularity, while maintaining cache coherence between the first processing unit and the second processing unit at a second granularity. The first granularity may be finer than the second granularity.
摘要翻译：提供了用于维护两个或多个异构处理器之间的高速缓存一致性的系统，方法和设备。根据一个实施例，这样的电子设备可以包括存储器，具有第一特征存储器使用率的第一处理单元和具有低于第一特征存储器使用率的第二特征存储器使用率的第二处理单元。第一和第二处理单元可以共享存储器的至少一部分，并且第一和第二处理单元中的一个或两个可以以第一粒度保持内部高速缓存一致性，同时保持第一处理单元和第二处理单元之间的高速缓存一致性以第二粒度。第一粒度可能比第二粒度更精细。

2. 发明授权

US08799553B2 Memory controller mapping on-the-fly 有权
标题翻译：内存控制器映射
公开(公告)号：US08799553B2
公开(公告)日：2014-08-05
申请号：US12895689
申请日：2010-09-30
申请人： Ian Hendry , Rajabali Koduri , Jeffry Gonion
发明人： Ian Hendry , Rajabali Koduri , Jeffry Gonion
IPC分类号： G06F12/06 , G06F17/30
CPC分类号： G06F3/0647 , G06F1/3203 , G06F1/3225 , G06F1/3275 , G06F3/0604 , G06F3/0625 , G06F3/065 , G06F3/0673 , G06F12/0292 , G06F12/06 , G06F12/0646 , G06F12/08 , G06F17/30147 , G06F2003/0697 , Y02D10/14 , Y02D50/20
摘要： Systems, methods, and devices for dynamically mapping and remapping memory when a portion of memory is activated or deactivated are provided. In accordance with an embodiment, an electronic device may include several memory banks, one or more processors, and a memory controller. The memory banks may store data in hardware memory locations and may be independently deactivated. The processors may request the data using physical memory addresses, and the memory controller may translate the physical addresses to hardware memory locations. The memory controller may use a first memory mapping function when a first number of memory banks is active and a second memory mapping function when a second number is active. When one of the memory banks is to be deactivated, the memory controller may copy data from only the memory bank that is to be deactivated to the active remainder of memory banks.
摘要翻译：提供了当存储器的一部分被激活或去激活时用于动态地映射和重映射存储器的系统，方法和设备。根据实施例，电子设备可以包括几个存储器组，一个或多个处理器和存储器控制器。存储体可以将数据存储在硬件存储器位置中，并且可以被独立地去激活。处理器可以使用物理存储器地址请求数据，并且存储器控制器可以将物理地址转换为硬件存储器位置。当第二数量有效时，存储器控制器可以使用第一存储器组的第一存储器映射功能和第二存储器映射功能。当存储器组中的一个被禁用时，存储器控制器可以将数据仅从要被去激活的存储器组复制到存储体的有效剩余部分。

3. 发明申请

US20110252200A1 COHERENT MEMORY SCHEME FOR HETEROGENEOUS PROCESSORS 有权
标题翻译：异构处理器的相关记忆方案
公开(公告)号：US20110252200A1
公开(公告)日：2011-10-13
申请号：US13082139
申请日：2011-04-07
申请人： Ian Hendry , Rajabali Koduri
发明人： Ian Hendry , Rajabali Koduri
IPC分类号： G06F12/08 , G06F12/02
CPC分类号： G06F12/0835 , G06F12/0831 , G06F12/1045
摘要： Systems, methods, and devices for maintaining cache coherence between two or more heterogeneous processors are provided. In accordance with one embodiment, such an electronic device may include memory, a first processing unit having a first characteristic memory usage rate, and a second processing unit having a second characteristic memory usage rate lower than the first. The first and second processing units may share at least a portion of the memory and one or both of the first and second processing units may maintain internal cache coherence at a first granularity, while maintaining cache coherence between the first processing unit and the second processing unit at a second granularity. The first granularity may be finer than the second granularity.
摘要翻译：提供了用于维护两个或多个异构处理器之间的高速缓存一致性的系统，方法和设备。根据一个实施例，这样的电子设备可以包括存储器，具有第一特征存储器使用率的第一处理单元和具有低于第一特征存储器使用率的第二特征存储器使用率的第二处理单元。第一和第二处理单元可以共享存储器的至少一部分，并且第一和第二处理单元中的一个或两个可以以第一粒度保持内部高速缓存一致性，同时保持第一处理单元和第二处理单元之间的高速缓存一致性以第二粒度。第一粒度可能比第二粒度更精细。

4. 发明申请

US20070257935A1 Advanced anti-aliasing with multiple graphics processing units 有权
标题翻译：具有多个图形处理单元的高级抗锯齿
公开(公告)号：US20070257935A1
公开(公告)日：2007-11-08
申请号：US11429078
申请日：2006-05-08
申请人： Rajabali Koduri , Gordon Elder , Jeffrey Golds
发明人： Rajabali Koduri , Gordon Elder , Jeffrey Golds
IPC分类号： G09G5/00
CPC分类号： G06T15/503 , G06F3/14 , G06T7/13 , G06T11/203 , G06T15/005 , G06T2210/08 , G06T2210/52 , G09G5/001 , G09G5/363
摘要： A method and apparatus for performing multisampling-based antialiasing in a system that includes first and second graphics processing unit (GPUs) that reduces the amount of data transferred between the GPUs and improves the efficiency with which such data is transferred. The first GPU renders a first version of a frame using a first multisampling pattern and the second GPU renders a second version of a frame in the second GPU using a second multisampling pattern. The second GPU identifies non-edge pixels in the second version of the frame. The pixels in the first version of the frame are then combined with only those pixels in the second version of the frame that have not been identified as non-edge pixels to generate a combined frame.
摘要翻译：一种在包括第一和第二图形处理单元（GPU）的系统中执行基于多采样的抗锯齿的方法和装置，其减少了在GPU之间传送的数据量并提高了传送这些数据的效率。第一GPU使用第一多采样模式呈现帧的第一版本，并且第二GPU使用第二多采样模式在第二GPU中呈现帧的第二版本。第二个GPU识别帧的第二个版本中的非边缘像素。然后，该帧的第一版本中的像素仅与尚未被识别为非边缘像素的帧的第二版本中的那些像素组合以生成组合帧。

5. 发明公开

US20230315305A1 APPARATUS AND METHOD TO IMPLEMENT CACHING AND COMPRESSION IN DRAM FOR CAPACITY IMPROVEMENT 审中-公开
公开(公告)号：US20230315305A1
公开(公告)日：2023-10-05
申请号：US17712098
申请日：2022-04-02
申请人： Abhishek Anil Sharma , Wilfred Gomes , Pushkar Ranade , Rajabali Koduri
发明人： Abhishek Anil Sharma , Wilfred Gomes , Pushkar Ranade , Rajabali Koduri
IPC分类号： G06F3/06 , G06F17/16
CPC分类号： G06F3/0622 , G06F3/0608 , G06F3/0659 , G06F3/0688 , G06F17/16
摘要： Method and apparatus to implement an integrated circuit (IC) device to perform compression/decompression operations. In one embodiment, the IC device includes a memory array containing a plurality of memory cells to store data and compression/decompression circuitry to perform compression operations on data to be written to the memory array and decompression operations on data read from the memory array. The memory array and the compression/decompression circuitry are integrated in a same die but at different die depth. At least a portion of the memory array overlaps a portion of the compression/decompression circuitry in a same x-y plane.

6. 发明申请

US20110252180A1 MEMORY CONTROLLER MAPPING ON-THE-FLY 有权
标题翻译：内存控制器映射
公开(公告)号：US20110252180A1
公开(公告)日：2011-10-13
申请号：US12895689
申请日：2010-09-30
申请人： Ian Hendry , Rajabali Koduri , Jeffry Gonion
发明人： Ian Hendry , Rajabali Koduri , Jeffry Gonion
IPC分类号： G06F12/10 , G06F1/32 , G06F12/08 , G06F12/00 , G06F12/02
CPC分类号： G06F3/0647 , G06F1/3203 , G06F1/3225 , G06F1/3275 , G06F3/0604 , G06F3/0625 , G06F3/065 , G06F3/0673 , G06F12/0292 , G06F12/06 , G06F12/0646 , G06F12/08 , G06F17/30147 , G06F2003/0697 , Y02D10/14 , Y02D50/20
摘要： Systems, methods, and devices for dynamically mapping and remapping memory when a portion of memory is activated or deactivated are provided. In accordance with an embodiment, an electronic device may include several memory banks, one or more processors, and a memory controller. The memory banks may store data in hardware memory locations and may be independently deactivated. The processors may request the data using physical memory addresses, and the memory controller may translate the physical addresses to hardware memory locations. The memory controller may use a first memory mapping function when a first number of memory banks is active and a second memory mapping function when a second number is active. When one of the memory banks is to be deactivated, the memory controller may copy data from only the memory bank that is to be deactivated to the active remainder of memory banks
摘要翻译：提供了当存储器的一部分被激活或去激活时用于动态地映射和重映射存储器的系统，方法和设备。根据实施例，电子设备可以包括几个存储器组，一个或多个处理器和存储器控制器。存储体可以将数据存储在硬件存储器位置中，并且可以被独立地去激活。处理器可以使用物理存储器地址请求数据，并且存储器控制器可以将物理地址转换为硬件存储器位置。当第二数量有效时，存储器控制器可以使用第一存储器组的第一存储器映射功能和第二存储器映射功能。当一个存储体被取消时，存储器控制器可以将数据从仅被要被去激活的存储体复制到存储体的有效剩余部分

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