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1. 发明申请

US20110055617A1 Hybrid Single and Dual Channel DDR Interface Scheme by Interleaving Address/Control Signals During Dual Channel Operation 有权
标题翻译：混合单通道和双通道DDR接口方案通过在双通道操作期间交错地址/控制信号
公开(公告)号：US20110055617A1
公开(公告)日：2011-03-03
申请号：US12547578
申请日：2009-08-26
申请人： Raghu Sankuratri , Michael Drop , Jian Mao
发明人： Raghu Sankuratri , Michael Drop , Jian Mao
IPC分类号： G06F1/04 , G06F12/00
CPC分类号： G06F13/1684
摘要： A memory structure is described. In one embodiment, the memory structure comprises a memory controller configured to receive a clock signal and to be coupled to a plurality of memory modules via a single address/control bus. The memory controller couples to each of the plurality of memory modules via a separate chip select signal for each memory module. The memory controller issues commands across the address/control bus to the memory modules in an interleaved fashion in accordance with the timing supplied by the clock. During a waiting period after issuance of a command to one memory module, the memory controller can issue commands to a different memory module.
摘要翻译：描述了存储器结构。在一个实施例中，存储器结构包括被配置为接收时钟信号并且经由单个地址/控制总线耦合到多个存储器模块的存储器控制器。存储器控制器经由用于每个存储器模块的单独芯片选择信号耦合到多个存储器模块中的每一个。存储器控制器根据时钟提供的定时以交错的方式将地址/控制总线上的命令发送到存储器模块。在向一个存储器模块发出命令之后的等待期间，存储器控制器可以向不同的存储器模块发出命令。

2. 发明申请

US20090219779A1 Dual Channel Memory Architecture Having a Reduced Interface Pin Requirements Using a Double Data Rate Scheme for the Address/Control Signals 有权
标题翻译：双通道存储器体系结构具有降低的接口引脚要求，使用双数据速率方案用于地址/控制信号
公开(公告)号：US20090219779A1
公开(公告)日：2009-09-03
申请号：US12039908
申请日：2008-02-29
申请人： Jian Mao , Raghu Sankuratri
发明人： Jian Mao , Raghu Sankuratri
IPC分类号： G11C8/18
CPC分类号： G06F13/1689 , G06F13/1684 , G06F13/4243 , Y02D10/14 , Y02D10/151
摘要： Apparatuses and methods for dual channel memory architecture with reduced interface pin requirements are presented. One memory architecture includes a memory controller, a first memory device coupled to the memory controller by a shared address bus and a first clock signal, and a second memory device coupled to the memory controller by the shared address bus and a second clock signal, where the polarity of the second clock signal is opposite of the first clock signal. A method for performing data transactions is presented. The method includes providing addressing signals over a shared address bus to a first memory device and a second memory device, providing clock signals to the memory devices which are reversed in polarity, where the clock signals are derived from a common clock signal, and transferring data to the memory devices over separate narrow data buses in an alternating manner based upon the clock signals.
摘要翻译：介绍了降低接口引脚要求的双通道存储架构的设备和方法。一个存储器架构包括存储器控制器，通过共享地址总线和第一时钟信号耦合到存储器控制器的第一存储器件，以及通过共享地址总线和第二时钟信号耦合到存储器控制器的第二存储器件，其中第二时钟信号的极性与第一时钟信号相反。提出了一种执行数据交易的方法。该方法包括通过共享地址总线向第一存储器件和第二存储器件提供寻址信号，向极性反转的存储器件提供时钟信号，其中时钟信号从公共时钟信号导出，并传送数据基于时钟信号以交替的方式通过单独的窄数据总线传送到存储器件。

3. 发明授权

US06735454B1 Method and apparatus for activating a high frequency clock following a sleep mode within a mobile station operating in a slotted paging mode 有权
标题翻译：用于在以时隙寻呼模式操作的移动台中的休眠模式之后激活高频时钟的方法和装置
公开(公告)号：US06735454B1
公开(公告)日：2004-05-11
申请号：US09434869
申请日：1999-11-04
申请人： Nicholas K. Yu , Kenneth David Easton , Raghu Sankuratri
发明人： Nicholas K. Yu , Kenneth David Easton , Raghu Sankuratri
IPC分类号： H04B116
CPC分类号： H04W52/0293 , H04W52/029 , Y02D70/122
摘要： A technique for activating an active-mode high frequency clock following a sleep period for use within a mobile station wherein selected components of the mobile station operate using a low power, low frequency sleep-mode clock during the sleep period and the faster high frequency active-mode clock during non-sleep periods. In one embodiment, the technique is implemented by a device having a wake-up estimation unit for estimating a wake up time using the sleep-mode clock and a frequency drift compensation unit for compensating for any error in the estimated wake up time caused by frequency drift in the sleep-mode clock. An off-set time compensation unit is also provided for compensating for a lack of precision in the low frequency sleep-mode clock resulting in a possible error in the estimated wake up time. The lack of precision can result in an initial timing off-set error at the beginning of the sleep period and an final timing off-set error at the end of the sleep period. Both the frequency drift compensation unit and the off-set time compensation unit employ a high frequency transition-mode clock signal for use in calculating the time required to adjust the wake-up time. The transition-mode clock, which may have the same frequency as the active-mode clock, is employed only at the beginning and end of the sleep period and is deactivated throughout most of the sleep period to reduce power consumption.
摘要翻译：一种用于在移动站内使用的睡眠周期之后激活活动模式高频时钟的技术，其中移动站的选定组件在休眠期间使用低功率，低频睡眠模式时钟和更快的高频活动在非睡眠期间的模式时钟。在一个实施例中，该技术由具有用于使用睡眠模式时钟估计唤醒时间的唤醒估计单元的装置和用于补偿由频率引起的估计唤醒时间中的任何误差的频率漂移补偿单元漂移在睡眠模式时钟。还提供了一种偏置时间补偿单元，用于补偿低频睡眠模式时钟的精度不足，导致估计的唤醒时间中的可能的误差。缺乏精确度可能导致睡眠周期开始时的初始定时偏移误差和睡眠周期结束时的最终定时偏移误差。频率漂移补偿单元和偏移时间补偿单元均采用高频转换模式时钟信号，用于计算调整唤醒时间所需的时间。可以具有与有源模式时钟相同的频率的转换模式时钟仅在睡眠周期的开始和结束时使用，并且在整个睡眠周期的大部分期间被去激活以减少功耗。

4. 发明授权

US08098539B2 Hybrid single and dual channel DDR interface scheme by interleaving address/control signals during dual channel operation 有权
标题翻译：混合单通道和双通道DDR接口方案通过在双通道操作期间交织地址/控制信号
公开(公告)号：US08098539B2
公开(公告)日：2012-01-17
申请号：US12547578
申请日：2009-08-26
申请人： Raghu Sankuratri , Michael Drop , Jian Mao
发明人： Raghu Sankuratri , Michael Drop , Jian Mao
IPC分类号： G11C8/00
CPC分类号： G06F13/1684
摘要： A memory structure is described. In one embodiment, the memory structure comprises a memory controller configured to receive a clock signal and to be coupled to a plurality of memory modules via a single address/control bus. The memory controller couples to each of the plurality of memory modules via a separate chip select signal for each memory module. The memory controller issues commands across the address/control bus to the memory modules in an interleaved fashion in accordance with the timing supplied by the clock. During a waiting period after issuance of a command to one memory module, the memory controller can issue commands to a different memory module.
摘要翻译：描述了存储器结构。在一个实施例中，存储器结构包括被配置为接收时钟信号并且经由单个地址/控制总线耦合到多个存储器模块的存储器控制器。存储器控制器经由用于每个存储器模块的单独芯片选择信号耦合到多个存储器模块中的每一个。存储器控制器根据时钟提供的定时以交错的方式将地址/控制总线上的命令发送到存储器模块。在向一个存储器模块发出命令之后的等待期间，存储器控制器可以向不同的存储器模块发出命令。

5. 发明授权

US07804735B2 Dual channel memory architecture having a reduced interface pin requirements using a double data rate scheme for the address/control signals 有权
标题翻译：双通道存储器架构使用针对地址/控制信号的双数据速率方案来减少接口引脚要求
公开(公告)号：US07804735B2
公开(公告)日：2010-09-28
申请号：US12039908
申请日：2008-02-29
申请人： Jian Mao , Raghu Sankuratri
发明人： Jian Mao , Raghu Sankuratri
IPC分类号： G11C8/00
CPC分类号： G06F13/1689 , G06F13/1684 , G06F13/4243 , Y02D10/14 , Y02D10/151
摘要： Apparatuses and methods for dual channel memory architecture with reduced interface pin requirements are presented. One memory architecture includes a memory controller, a first memory device coupled to the memory controller by a shared address bus and a first clock signal, and a second memory device coupled to the memory controller by the shared address bus and a second clock signal, where the polarity of the second clock signal is opposite of the first clock signal. A method for performing data transactions is presented. The method includes providing addressing signals over a shared address bus to a first memory device and a second memory device, providing clock signals to the memory devices which are reversed in polarity, where the clock signals are derived from a common clock signal, and transferring data to the memory devices over separate narrow data buses in an alternating manner based upon the clock signals.
摘要翻译：介绍了降低接口引脚要求的双通道存储架构的设备和方法。一个存储器架构包括存储器控制器，通过共享地址总线和第一时钟信号耦合到存储器控制器的第一存储器件，以及通过共享地址总线和第二时钟信号耦合到存储器控制器的第二存储器件，其中第二时钟信号的极性与第一时钟信号相反。提出了一种执行数据交易的方法。该方法包括通过共享地址总线向第一存储器件和第二存储器件提供寻址信号，向极性反转的存储器件提供时钟信号，其中时钟信号从公共时钟信号导出，并传送数据基于时钟信号以交替的方式通过单独的窄数据总线传送到存储器件。

6. 发明申请

US20050114725A1 Calibrating an integrated circuit to an electronic device 审中-公开
标题翻译：将集成电路校准到电子设备
公开(公告)号：US20050114725A1
公开(公告)日：2005-05-26
申请号：US10722350
申请日：2003-11-25
申请人： Jagrut Patel , Dexter Chun , Gregory Bullard , Raghu Sankuratri , Rajeev Prabhakaran , Sanat Kapoor
发明人： Jagrut Patel , Dexter Chun , Gregory Bullard , Raghu Sankuratri , Rajeev Prabhakaran , Sanat Kapoor
IPC分类号： G01R35/00 , G06F1/14 , G06F1/04
CPC分类号： G01R35/005
摘要： Systems and techniques are disclosed relating to calibrating an integrated circuit to an electronic component. The systems and techniques include an integrated circuit configured to generate a system clock and an external clock having a programmable delay from the system clock. The integrated circuit may also be configured to provide the external clock to the electronic component to support communications therewith, communicate with the electronic component, and calibrate the external clock delay as a function of the communications.
摘要翻译：公开了关于将集成电路校准到电子部件的系统和技术。该系统和技术包括被配置为产生系统时钟的集成电路和具有来自系统时钟的可编程延迟的外部时钟。集成电路还可以被配置为向电子部件提供外部时钟以支持与其通信，与电子部件通信，并且根据通信校准外部时钟延迟。

7. 发明授权

US08325525B2 Dual channel memory architecture having reduced interface pin requirements using a double data rate scheme for the address/control signals 有权
标题翻译：双通道存储器架构使用双数据速率方案来减少接口引脚要求，用于地址/控制信号
公开(公告)号：US08325525B2
公开(公告)日：2012-12-04
申请号：US12860441
申请日：2010-08-20
申请人： Jian Mao , Raghu Sankuratri
发明人： Jian Mao , Raghu Sankuratri
IPC分类号： G11C16/04
CPC分类号： G06F13/1689 , G06F13/1684 , G06F13/4243 , Y02D10/14 , Y02D10/151
摘要： Apparatuses and methods for dual channel memory architecture with reduced interface pin requirements are presented. One memory architecture includes a memory controller, a first memory device coupled to the memory controller by a shared address bus and a first clock signal, and a second memory device coupled to the memory controller by the shared address bus and a second clock signal, where the polarity of the second clock signal is opposite of the first clock signal. A method for performing data transactions is presented. The method includes providing addressing signals over a shared address bus to a first memory device and a second memory device, providing clock signals to the memory devices which are reversed in polarity, where the clock signals are derived from a common clock signal, and transferring data to the memory devices over separate narrow data buses in an alternating manner based upon the clock signals.
摘要翻译：介绍了降低接口引脚要求的双通道存储架构的设备和方法。一个存储器架构包括存储器控制器，通过共享地址总线和第一时钟信号耦合到存储器控制器的第一存储器件，以及通过共享地址总线和第二时钟信号耦合到存储器控制器的第二存储器件，其中第二时钟信号的极性与第一时钟信号相反。提出了一种执行数据交易的方法。该方法包括通过共享地址总线向第一存储器件和第二存储器件提供寻址信号，向极性反转的存储器件提供时钟信号，其中时钟信号从公共时钟信号导出，并传送数据基于时钟信号以交替的方式通过单独的窄数据总线传送到存储器件。

8. 发明申请

US20100318730A1 Dual Channel Memory Architecture Having Reduced Interface Pin Requirements Using a Double Data Rate Scheme for the Address/Control Signals 有权
标题翻译：双通道存储器架构，使用双数据速率方案降低接口引脚要求的地址/控制信号
公开(公告)号：US20100318730A1
公开(公告)日：2010-12-16
申请号：US12860441
申请日：2010-08-20
申请人： Jian Mao , Raghu Sankuratri
发明人： Jian Mao , Raghu Sankuratri
IPC分类号： G06F12/00 , G06F1/04 , G06F12/02
CPC分类号： G06F13/1689 , G06F13/1684 , G06F13/4243 , Y02D10/14 , Y02D10/151
摘要： Apparatuses and methods for dual channel memory architecture with reduced interface pin requirements are presented. One memory architecture includes a memory controller, a first memory device coupled to the memory controller by a shared address bus and a first clock signal, and a second memory device coupled to the memory controller by the shared address bus and a second clock signal, where the polarity of the second clock signal is opposite of the first clock signal. A method for performing data transactions is presented. The method includes providing addressing signals over a shared address bus to a first memory device and a second memory device, providing clock signals to the memory devices which are reversed in polarity, where the clock signals are derived from a common clock signal, and transferring data to the memory devices over separate narrow data buses in an alternating manner based upon the clock signals.
摘要翻译：介绍了降低接口引脚要求的双通道存储架构的设备和方法。一个存储器架构包括存储器控制器，通过共享地址总线和第一时钟信号耦合到存储器控制器的第一存储器件，以及通过共享地址总线和第二时钟信号耦合到存储器控制器的第二存储器件，其中第二时钟信号的极性与第一时钟信号相反。提出了一种执行数据交易的方法。该方法包括通过共享地址总线向第一存储器件和第二存储器件提供寻址信号，向极性反转的存储器件提供时钟信号，其中时钟信号从公共时钟信号导出，并传送数据基于时钟信号以交替的方式通过单独的窄数据总线传送到存储器件。

9. 发明授权

US06754509B1 Mobile communication device having dual micro processor architecture with shared digital signal processor and shared memory 有权
标题翻译：具有双微处理器架构的移动通信设备，具有共享数字信号处理器和共享存储器
公开(公告)号：US06754509B1
公开(公告)日：2004-06-22
申请号：US09475336
申请日：1999-12-30
申请人： Safi Khan , Sanjay Jha , Albert Scott Ludwin , Mehraban Iraninejad , Raghu Sankuratri , Chauhung Lee , Richard Higgins , Nicholas K. Yu
发明人： Safi Khan , Sanjay Jha , Albert Scott Ludwin , Mehraban Iraninejad , Raghu Sankuratri , Chauhung Lee , Richard Higgins , Nicholas K. Yu
IPC分类号： H04B138
CPC分类号： H04B1/3805 , H04M1/72522
摘要： The dual microprocessor system includes one microprocessor configured to perform wireless telephony functions and another configured to perform personal digital assistant (PDA) functions and other non-telephony functions. A memory system and a digital signal processor (DSP) are shared by the microprocessors. By providing a shared memory system, data required by both data microprocessors is conveniently available to both of the microprocessors and their peripheral components thereby eliminating the need to provide separate memory subsystems and further eliminating the need to transfer data back and forth between the separate memory subsystems. By providing a shared DSP, separate DSP devices need not be provided, yet both microprocessors can take advantage of the processing power of the DSP. In a specific example described herein, the microprocessors selectively program the DSP to perform, for example, vocoder functions, voice recognition functions, handwriting recognition functions, and the like.
摘要翻译：双微处理器系统包括配置成执行无线电话功能的一个微处理器，以及被配置为执行个人数字助理（PDA）功能和其他非电话功能的另一微处理器系统。存储器系统和数字信号处理器（DSP）由微处理器共享。通过提供共享存储器系统，两个数据微处理器所需的数据对于微处理器及其外围组件都是便利的，因此消除了提供分开的存储器子系统的需要，并且进一步消除了在分开的存储器子系统之间来回传送数据的需要。通过提供共享DSP，不需要提供独立的DSP设备，但是这两个微处理器都可以利用DSP的处理能力。在本文描述的具体示例中，微处理器选择性地编程DSP以执行例如声码器功能，语音识别功能，手写识别功能等。

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