会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 2. 发明授权
    • Multiferroic antenna and transmitter
    • 多层天线和发射机
    • US08803751B1
    • 2014-08-12
    • US12885817
    • 2010-09-20
    • Robert J. MillerWilliam Preston GerenStephen P. Hubbell
    • Robert J. MillerWilliam Preston GerenStephen P. Hubbell
    • H01Q1/00H01Q7/06H01Q3/44H01L41/00
    • H01Q7/06H01Q1/28H01Q3/44
    • A multiferroic element may include a substrate formed on an electrically conductive ground plane. The substrate may be formed from a material having a predetermined elastic modulus. A layer of piezoelectric material may be formed on the substrate. A layer of magnetostrictive material may be bonded to the layer of piezoelectric material. A mechanical strain is created in the layer of piezoelectric material in response to a voltage signal being applied to the multiferroic element. The mechanical strain in the layer of piezoelectric material causes a mechanical strain in the layer of magnetostrictive material to produce a radio frequency magnetic field that is proportional to the voltage signal for generating a radio frequency electromagnetic wave. The predetermined elastic modulus of the substrate is substantially lower than an elastic modulus of the layer of piezoelectric material.
    • 多铁元件可以包括形成在导电接地平面上的衬底。 衬底可以由具有预定弹性模量的材料形成。 可以在基板上形成压电材料层。 一层磁致伸缩材料可以结合到压电材料层上。 响应于施加到多铁元件的电压信号,在压电材料层中产生机械应变。 压电材料层中的机械应变引起磁致伸缩材料层中的机械应变,产生与产生射频电磁波的电压信号成比例的射频磁场。 基板的预定弹性模量基本上低于压电材料层的弹性模量。
    • 3. 发明授权
    • Semiconductor device having localized extremely thin silicon on insulator channel region
    • 半导体器件具有局部极薄的绝缘体上硅沟道区域
    • US08685847B2
    • 2014-04-01
    • US12912897
    • 2010-10-27
    • Amlan MajumdarRobert J. MillerMuralidhar Ramachandran
    • Amlan MajumdarRobert J. MillerMuralidhar Ramachandran
    • H01L21/425
    • H01L29/66545H01L29/66772H01L29/7848H01L29/78618H01L29/78654
    • A method of forming a transistor device includes forming a dummy gate stack structure over an SOI starting substrate, comprising a bulk layer, a global BOX layer over the bulk layer, and an SOI layer over the global BOX layer. Self-aligned trenches are formed completely through portions of the SOI layer and the global BOX layer at source and drain regions. Silicon is epitaxially regrown in the source and drain regions, with a local BOX layer re-established in the epitaxially regrown silicon, adjacent to the global BOX layer. A top surface of the local BOX layer is below a top surface of the global BOX layer. Embedded source and drain stressors are formed in the source and drain regions, adjacent a channel region. Silicide contacts are formed on the source and drain regions. The dummy gate stack structure is removed, and a final gate stack structure is formed.
    • 一种形成晶体管器件的方法包括:在SOI起始衬底上形成虚拟栅极堆叠结构,其包括体层,体层上的全局BOX层以及全局BOX层上的SOI层。 自对准沟槽通过SOI层和源极和漏极区域的全局BOX层的部分完全形成。 硅在源极和漏极区域中外延再生长,在外延重新生长的硅中重新建立局部BOX层,邻近全局BOX层。 本地BOX层的顶表面位于全局BOX层的顶表面之下。 在源极和漏极区域中形成嵌入的源极和漏极应力源,邻近沟道区域。 在源极和漏极区域上形成硅化物接触。 去除虚拟栅极堆叠结构,形成最终的栅极堆叠结构。
    • 9. 发明授权
    • Substrate solution for back gate controlled SRAM with coexisting logic devices
    • 用于具有共存逻辑器件的背栅控制SRAM的衬底解决方案
    • US07838942B2
    • 2010-11-23
    • US12144272
    • 2008-06-23
    • Robert H. DennardWilfried E. HaenschArvind KumarRobert J. Miller
    • Robert H. DennardWilfried E. HaenschArvind KumarRobert J. Miller
    • H01L29/76
    • H01L27/1108
    • A semiconductor structure that includes at least one logic device region and at least one static random access memory (SRAM) device region wherein each device region includes a double gated field effect transistor (FET) wherein the back gate of each of the FET devices is doped to a specific level so as to improve the performance of the FET devices within the different device regions is provided. In particular, the back gate within the SRAM device region is more heavily doped than the back gate within the logic device region. In order to control short channel effects, the FET device within the logic device region includes a doped channel, while the FET device within the SRAM device region does not. A none uniform lateral doping profile with a low net doping beneath the source/drain regions and a high net doping underneath the channel would provide additional SCE control for the logic device.
    • 一种半导体结构,其包括至少一个逻辑器件区域和至少一个静态随机存取存储器(SRAM)器件区域,其中每个器件区域包括双门控场效应晶体管(FET),其中每个FET器件的背栅极掺杂 提供了特定的水平,以提高不同器件区域内的FET器件的性能。 特别地,SRAM器件区域内的背栅极比逻辑器件区域内的后栅极重掺杂。 为了控制短沟道效应,逻辑器件区域内的FET器件包括掺杂沟道,而SRAM器件区域内的FET器件不是。 在源极/漏极区域之下具有低净掺杂的非均匀横向掺杂分布和在沟道下方的高净掺杂将为逻辑器件提供附加的SCE控制。