专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20170286247A1 APPARATUS AND METHOD FOR A SCALABLE TEST ENGINE 审中-公开
公开(公告)号：US20170286247A1
公开(公告)日：2017-10-05
申请号：US15089448
申请日：2016-04-01
申请人： LAKSHMINARAYANA PAPPU , ROBERT DE GRUIJL , SUKETU U. BHATT , ROBERT P. ADLER , R SELVAKUMAR RAJA GOPAL , RIUS TANADI
发明人： LAKSHMINARAYANA PAPPU , ROBERT DE GRUIJL , SUKETU U. BHATT , ROBERT P. ADLER , R SELVAKUMAR RAJA GOPAL , RIUS TANADI
IPC分类号： G06F11/273 , G01R31/319 , G06F17/50
CPC分类号： G06F11/2736 , G01R31/31915 , G06F17/5045 , G06F2217/14 , G06F2217/66
摘要： An apparatus and method are described for a scalable testing agent. For example, one embodiment of a scalable test engine comprises: an input interface to receive commands and/or data from a processor core or an external test system, the commands and/or data to specify one or more test operations to be performed on one or more intellectual property (IP) blocks of a chip; a first circuit to establish communication with an IP block over an interconnect fabric, the first circuit to transmit the one or more test operations to the IP block responsive to the received commands and/or data, the IP block to process the test operations and generate results; and a second circuit to receive the results from the IP block over the interconnect fabric, the results to be provided from the second circuit to the processor core and/or the external test system for analysis.

2. 发明申请

US20180121574A1 Method, Apparatus And System For Automatically Performing End-To-End Channel Mapping For An Interconnect 审中-公开
公开(公告)号：US20180121574A1
公开(公告)日：2018-05-03
申请号：US15338639
申请日：2016-10-31
申请人： Krishnan Srinivasan , Robert P. Adler , Eric A. Geisler , Robert De Gruijl , Jay Tomlinson
发明人： Krishnan Srinivasan , Robert P. Adler , Eric A. Geisler , Robert De Gruijl , Jay Tomlinson
IPC分类号： G06F17/50 , H04L29/12 , G06F13/42 , G06F13/40
CPC分类号： G06F17/505 , G06F13/4068 , G06F13/4282 , G06F2213/0026 , H04L61/2007
摘要： In one embodiment, a design tool for designing a system on chip (SoC) includes hardware mapping logic to automatically generate a channel mapping for a path between a first intellectual property (IP) logic of the SoC and a second IP logic of the SoC. The hardware mapping logic, based at least in part on user input of a source channel associated with the first IP logic, a sink channel associated with the second IP logic and at least one derivation parameter, is to generate the channel mapping according to one of a plurality of derivation algorithms. Other embodiments are described and claimed.

3. 发明申请

US20110096880A1 Lossless Transfer Of Events Across Clock Domains 有权
标题翻译：跨越时钟域的事件的无损传输
公开(公告)号：US20110096880A1
公开(公告)日：2011-04-28
申请号：US10562342
申请日：2004-06-25
申请人： Otto Steinbusch , Marino Strik , Robert DE Gruijl
发明人： Otto Steinbusch , Marino Strik , Robert DE Gruijl
IPC分类号： H04L7/00
CPC分类号： H04L7/02
摘要： Transfer circuits (200, 400, 500) for monitoring in a monitor clock domain target events that occur in a target clock domain (170) are disclosed. Some embodiments (200) impose significant constraints on the domain clocks and include: an event detector (210); a sending circuit (220) that changes the value of a request signal (150) with each event; and a receiving circuit (230) that detects changes in the request signal. Other embodiments work for a broader range of clocks and include: a counter (410) that generates an incremental count (415) of event occurrences while a transfer is taking place; sending and receiving registers (420, 430, 530) for the incremental count; the request sending and receiving circuits (220, 230), where the request signal changes value for each transfer of the incremental count; and sending and receiving circuits (470, 480) for an acknowledgement signal.
摘要翻译：公开了用于在监视时钟域中监视目标时钟域（170）中发生的目标事件的传输电路（200,400,500）。一些实施例（200）对域时钟施加明显的限制，并且包括：事件检测器（210）; 发送电路（220），其用每个事件改变请求信号（150）的值; 以及检测请求信号的变化的接收电路（230）。其他实施例适用于更广泛的时钟范围，并且包括：计数器（410），其在发生转移时产生事件发生的增量计数（415）; 发送和接收用于增量计数的寄存器（420,430,530）; 所述请求发送和接收电路（220,230），其中所述请求信号改变每次所述递增计数的传送的值; 以及用于确认信号的发送和接收电路（470,480）。

4. 发明授权

US10042729B2 Apparatus and method for a scalable test engine 有权
公开(公告)号：US10042729B2
公开(公告)日：2018-08-07
申请号：US15089448
申请日：2016-04-01
申请人： Lakshminarayana Pappu , Robert De Gruijl , Suketu U. Bhatt , Robert P. Adler , R Selvakumar Raja Gopal , Rius Tanadi
发明人： Lakshminarayana Pappu , Robert De Gruijl , Suketu U. Bhatt , Robert P. Adler , R Selvakumar Raja Gopal , Rius Tanadi
IPC分类号： G06F11/273 , G06F17/50 , G01R31/319
摘要： An apparatus and method are described for a scalable testing agent. For example, one embodiment of a scalable test engine comprises: an input interface to receive commands and/or data from a processor core or an external test system, the commands and/or data to specify one or more test operations to be performed on one or more intellectual property (IP) blocks of a chip; a first circuit to establish communication with an IP block over an interconnect fabric, the first circuit to transmit the one or more test operations to the IP block responsive to the received commands and/or data, the IP block to process the test operations and generate results; and a second circuit to receive the results from the IP block over the interconnect fabric, the results to be provided from the second circuit to the processor core and/or the external test system for analysis.

5. 发明申请

US20180089342A1 METHOD, APPARATUS AND SYSTEM FOR AUTOMATICALLY DERIVING PARAMETERS FOR AN INTERCONNECT 审中-公开
公开(公告)号：US20180089342A1
公开(公告)日：2018-03-29
申请号：US15279725
申请日：2016-09-29
申请人： Krishnan Srinivasan , Robert P. Adler , Robert De Gruijl , Jay Tomlinson , Eric A. Geisler
发明人： Krishnan Srinivasan , Robert P. Adler , Robert De Gruijl , Jay Tomlinson , Eric A. Geisler
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5077 , G06F2217/68
摘要： In one embodiment, a design tool for designing a system on chip (SoC) includes hardware logic to generate one or more configuration files for a fabric of a SoC to be designed by the design tool. This logic is configured, based at least in part on user input, to generate the one or more configuration files, according to at least one of: automatic derivation of all parameters of the fabric, according to a first user selection; manual input by a user of at least some parameters of the fabric and automatic derivation of at least other parameters of the fabric, according to a second user selection; and manual input by the user of the all parameters of the fabric, according to a third user selection. Other embodiments are described and claimed.

6. 发明申请

US20150007189A1 SERVICE RATE REDISTRIBUTION FOR CREDIT-BASED ARBITRATION 审中-公开
标题翻译：基于信用仲裁的服务费率重新分配
公开(公告)号：US20150007189A1
公开(公告)日：2015-01-01
申请号：US14126899
申请日：2013-06-29
申请人： Robert De Gruijl , Michael T. Klinglesmith
发明人： Robert De Gruijl , Michael T. Klinglesmith
IPC分类号： G06F9/50
CPC分类号： G06F9/5011 , H04L41/0896 , H04L47/39
摘要： A particular requester of three or more requesters of a shared system resource is determined to be inactive. Each of the three or more requesters is allocated a respective service rate that each represents a corresponding share of available bandwidth of the system resource and the respective service rate of the particular requester is a first service rate that represents a first share of the bandwidth. Portions of the first share of the bandwidth are reallocated to each active requester in the three or more requesters to distribute the first portion of the bandwidth according to the relative services rates of the active requesters while the particular requester remains inactive.
摘要翻译：共享系统资源的三个或更多请求者的特定请求者被确定为不活动。三个或更多请求者中的每一个被分配相应的服务速率，每个服务速率表示系统资源的可用带宽的相应份额，并且特定请求者的相应服务速率是表示带宽的第一共享的第一服务速率。将带宽的第一份额的部分重新分配给三个或更多个请求者中的每个活动请求者，以在特定请求者保持不活动时根据活动请求者的相对服务速率分配带宽的第一部分。

7. 发明授权

US08400188B2 Methods, systems and arrangements for edge detection 有权
标题翻译：边缘检测的方法，系统和布置
公开(公告)号：US08400188B2
公开(公告)日：2013-03-19
申请号：US12922456
申请日：2009-03-16
申请人： Robert de Gruijl
发明人： Robert de Gruijl
IPC分类号： H03K5/22 , H03L7/00
CPC分类号： H03K5/1534
摘要： A variety of edge-detection related devices, methods and systems are implemented in various fashions. One implementation is directed to an edge detector circuit for detecting an edge of an input signal and producing an output level-sensitive signal that is synchronous to a clock signal having an active edge corresponding to a transition from a first-signal level to a second-signal level. A first flip-flop has the input signal as a clock input and produces an internal level-sensitive signal and is reset by the output level-sensitive signal. Logic passes the level-sensitive signal when the clock signal is at the second-signal level and blocks the internal level-sensitive signal when the clock signal is at the first-signal level. A second flip-flop is set by the passed internal level-sensitive signal to produce the output level-sensitive signal. The second flip-flop is cleared in response to the output level-sensitive signal, a reset input and the clock signal.
摘要翻译：各种边缘检测相关设备，方法和系统以各种方式实现。一种实施方式涉及用于检测输入信号的边沿并产生与具有对应于从第一信号电平到第二信号电平的转变的有效边沿的时钟信号同步的输出电平敏感信号的边缘检测器电路，信号电平。第一触发器具有作为时钟输入的输入信号，并产生内部电平敏感信号，并由输出电平敏感信号复位。当时钟信号处于第二信号电平时，逻辑通过电平敏感信号，并且当时钟信号处于第一信号电平时阻塞内部电平敏感信号。第二个触发器由传递的内部电平敏感信号设置，以产生输出电平敏感信号。响应于输出电平敏感信号，复位输入和时钟信号，第二个触发器被清零。

8. 发明授权

US08339157B2 Methods, circuits, systems and arrangements for undriven or driven pins 有权
标题翻译：方法，电路，系统和未驱动或驱动引脚的布置
公开(公告)号：US08339157B2
公开(公告)日：2012-12-25
申请号：US12922661
申请日：2009-03-16
申请人： Robert de Gruijl
发明人： Robert de Gruijl
IPC分类号： H03K19/00 , H03K19/0175
CPC分类号： H03K19/0008 , H03K5/003 , H03K19/1731
摘要： Input/Output (I/O) pin circuits, devices, methods and systems are implemented in various fashions. According to one such method, a valid signal level is provided for a pin of an integrated circuit (IC) die. Responsive to a reset signal, a first mode (304) is entered where one of a pull-up circuit or pull-down circuit is enabled (308, 310) to set the pin to the valid signal level. A change in signal level of the pin that is a deviation from the valid signal level is detected (312). Responsive to detecting the change, a second mode (314) is entered where the one of a pull-up circuit or pull-down circuit is disabled (316).
摘要翻译：输入/输出（I / O）引脚电路，器件，方法和系统以各种方式实现。根据一种这样的方法，为集成电路（IC）管芯的引脚提供有效的信号电平。响应于复位信号，进入第一模式（304），其中上拉电路或下拉电路中的一个被使能（308,310），以将引脚设置为有效信号电平。检测到与有效信号电平的偏差的引脚的信号电平的变化（312）。响应于检测变化，进入第二模式（314），其中上拉电路或下拉电路中的一个被禁用（316）。

9. 发明授权

US08284879B2 Lossless transfer of events across clock domains 有权
标题翻译：跨时钟域的事件无损传输
公开(公告)号：US08284879B2
公开(公告)日：2012-10-09
申请号：US10562342
申请日：2004-06-25
申请人： Otto Steinbusch , Marino Strik , Robert De Gruijl
发明人： Otto Steinbusch , Marino Strik , Robert De Gruijl
IPC分类号： H04L7/02 , H04L7/00
CPC分类号： H04L7/02
摘要： Transfer circuits (200, 400, 500) for monitoring in a monitor clock domain target events that occur in a target clock domain (170) are disclosed. Some embodiments (200) impose significant constraints on the domain clocks and include: an event detector (210); a sending circuit (220) that changes the value of a request signal (150) with each event; and a receiving circuit (230) that detects changes in the request signal. Other embodiments work for a broader range of clocks and include: a counter (410) that generates an incremental count (415) of event occurrences while a transfer is taking place; sending and receiving registers (420, 430, 530) for the incremental count; the request sending and receiving circuits (220, 230), where the request signal changes value for each transfer of the incremental count; and sending and receiving circuits (470, 480) for an acknowledgement signal.
摘要翻译：公开了用于在监视时钟域中监视目标时钟域（170）中发生的目标事件的传输电路（200,400,500）。一些实施例（200）对域时钟施加明显的限制，并且包括：事件检测器（210）; 发送电路（220），其用每个事件改变请求信号（150）的值; 以及检测请求信号的变化的接收电路（230）。其他实施例适用于更广泛的时钟范围，并且包括：计数器（410），其在发生转移时产生事件发生的增量计数（415）; 发送和接收用于增量计数的寄存器（420,430,530）; 所述请求发送和接收电路（220,230），其中所述请求信号改变每次所述递增计数的传送的值; 以及用于确认信号的发送和接收电路（470,480）。

10. 发明申请

US20110018585A1 METHODS, SYSTEMS AND ARRANGEMENTS FOR EDGE DETECTION 有权
标题翻译：方法，系统和边缘检测的安排
公开(公告)号：US20110018585A1
公开(公告)日：2011-01-27
申请号：US12922456
申请日：2009-03-16
申请人： Robert de Gruijl
发明人： Robert de Gruijl
IPC分类号： H03K5/00
CPC分类号： H03K5/1534
摘要： A variety of edge-detection related devices, methods and systems are implemented in various fashions. One implementation is directed to an edge detector circuit (100) for detecting an edge of an input signal and producing an output level-sensitive signal that is synchronous to a clock signal having an active edge corresponding to a transition from a first-signal level to a second-signal level. A first flip-flop (102) has the input signal as a clock input and produces an internal level-sensitive signal and is reset by the output level-sensitive signal. Logic passes (104) the level-sensitive signal when the clock signal is at the second-signal level and blocks the internal level-sensitive signal when the clock signal is at the first-signal level. A second flip-flop (106) is set by the passed internal level-sensitive signal to produce the output level-sensitive signal. The second flip-flop (106) is cleared in response to the output level-sensitive signal, a reset input and the clock signal.
摘要翻译：各种边缘检测相关设备，方法和系统以各种方式实现。一种实施方式涉及用于检测输入信号的边沿并产生与具有对应于从第一信号电平到第一信号电平的转换的有效边沿的时钟信号同步的输出电平敏感信号的边缘检测器电路（100）第二信号电平。第一触发器（102）将输入信号作为时钟输入，并产生内部电平敏感信号，并由输出电平敏感信号复位。当时钟信号处于第二信号电平时，逻辑通过（104）电平敏感信号，并且当时钟信号处于第一信号电平时阻塞内部电平敏感信号。第二触发器（106）由传递的内部电平敏感信号设置，以产生输出电平敏感信号。响应于输出电平敏感信号，复位输入和时钟信号，第二触发器（106）被清零。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式