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1. 发明授权

US08495301B1 System and method for scatter gather cache processing 有权
标题翻译：用于散射收集缓存处理的系统和方法
公开(公告)号：US08495301B1
公开(公告)日：2013-07-23
申请号：US12939128
申请日：2010-11-03
申请人： Praveen Alexander , Cheng Yi , Tao Zhong , David J. Clinton , Gary Nichols
发明人： Praveen Alexander , Cheng Yi , Tao Zhong , David J. Clinton , Gary Nichols
IPC分类号： G06F13/00
CPC分类号： G06F13/28
摘要： A scatter gather cache system and method are provided, which increase performance of scatter-gather DMA operations by reducing the time taken by the DMA engine to perform a logical to physical address translation. This is done primarily by two-dimensional caching of scatter-gather elements of selected scatter-gather lists using a novel indexing, line swapping and replacement methodology. The cache can also include a context victim table (CVT) for storing scatter-gather list contexts from evicted cache entries and also allows for pre-fetching of SGL elements from Scatter-Gather Lists (SGL). It also provides coherency support when there are multiple instances of the cache accessing the same memory space.
摘要翻译：提供了散射收集缓存系统和方法，通过减少DMA引擎执行逻辑到物理地址转换所花费的时间，从而提高了分散收集DMA操作的性能。这主要通过使用新颖的索引，线交换和替换方法，对所选分散收集列表的散点收集元素进行二维缓存。高速缓存还可以包括用于从驱逐的高速缓存条目存储分散收集列表上下文的上下文受害表（CVT），并且还允许从分散集合列表（SGL）中预取SGL元素。当缓存访问相同内存空间的多个实例时，它还提供一致性支持。

2. 发明授权

US08176252B1 DMA address translation scheme and cache with modified scatter gather element including SG list and descriptor tables 有权
标题翻译： DMA地址转换方案和具有修改的散列收集元素的缓存，包括SG列表和描述符表
公开(公告)号：US08176252B1
公开(公告)日：2012-05-08
申请号：US12203455
申请日：2008-09-03
申请人： Praveen Alexander , Heng Liao
发明人： Praveen Alexander , Heng Liao
IPC分类号： G06F13/00
CPC分类号： G06F13/28
摘要： A scatter gather element based caching system is provided along with a modified scatter gather element, that supports efficient logical to physical address translation for arbitrarily aligned and arbitrarily sized fragment (segment) based memory management schemes. This is different from modern CPU implementations with MMUs that support page-based implementations. A primary application of embodiments of the present invention is in DMA applications. The system enables frequent switching of contexts between I/Os using a novel caching technique. An embodiment of the present invention also includes the modification of the conventional scatter-gather element used in DMA for supporting multiple memory spaces, backward list traversals, better error recovery and debugging.
摘要翻译：提供了一种基于散点收集元素的高速缓存系统以及修改的分散收集元素，其支持用于任意对齐和任意大小的基于片段（片段）的存储器管理方案的有效的逻辑到物理地址转换。这与支持基于页面实现的MMU的现代CPU实现不同。本发明的实施例的主要应用是在DMA应用中。该系统允许使用新颖的缓存技术在I / O之间频繁切换上下文。本发明的一个实施例还包括用于支持多个存储空间的DMA中常规散射聚集元件的改进，后向列表遍历，更好的错误恢复和调试。

3. 发明授权

US08271700B1 Logical address direct memory access with multiple concurrent physical ports and internal switching 有权
标题翻译：具有多个并发物理端口和内部交换的逻辑地址直接内存访问
公开(公告)号：US08271700B1
公开(公告)日：2012-09-18
申请号：US13012296
申请日：2011-01-24
申请人： Babysaroja Annem , David J. Clinton , Praveen Alexander
发明人： Babysaroja Annem , David J. Clinton , Praveen Alexander
IPC分类号： G06F13/28
CPC分类号： G06F13/28 , G06F2213/0038
摘要： A DMA engine is provided that is suitable for higher performance System On a Chip (SOC) devices that have multiple concurrent on-chip/off-chip memory spaces. The DMA engine operates either on logical addressing method or physical addressing method and provides random and sequential mapping function from logical address to physical address while supporting frequent context switching among a large number of logical address spaces. Embodiments of the present invention utilize per direction (source-destination) queuing and an internal switch to support non-blocking concurrent transfer of data on multiple directions. A caching technique can be incorporated to reduce the overhead of address translation.
摘要翻译：提供了一种适用于具有多个并行片上/片外存储空间的高性能片上系统（SOC）器件的DMA引擎。 DMA引擎以逻辑寻址方法或物理寻址方式进行操作，并提供从逻辑地址到物理地址的随机和顺序映射功能，同时支持大量逻辑地址空间之间的频繁上下文切换。本发明的实施例利用每个方向（源 - 目的地）排队和内部交换机来支持多个方向上数据的非阻塞并发传输。可以结合缓存技术来减少地址转换的开销。

4. 发明授权

US07877524B1 Logical address direct memory access with multiple concurrent physical ports and internal switching 有权
标题翻译：具有多个并发物理端口和内部交换的逻辑地址直接内存访问
公开(公告)号：US07877524B1
公开(公告)日：2011-01-25
申请号：US12277194
申请日：2008-11-24
申请人： Babysaroja Annem , Heng Liao , Zhongzhi Liu , Praveen Alexander
发明人： Babysaroja Annem , Heng Liao , Zhongzhi Liu , Praveen Alexander
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A DMA engine is provided that is suitable for higher performance System On a Chip (SOC) devices that have multiple concurrent on-chip/off-chip memory spaces. The DMA engine operates either on logical addressing method or physical addressing method and provides random and sequential mapping function from logical address to physical address while supporting frequent context switching among a large number of logical address spaces. Embodiments of the present invention utilize per direction (source-destination) queuing and an internal switch to support non-blocking concurrent transfer of data on multiple directions. A caching technique can be incorporated to reduce the overhead of address translation.
摘要翻译：提供了一种适用于具有多个并行片上/片外存储空间的高性能片上系统（SOC）器件的DMA引擎。 DMA引擎以逻辑寻址方法或物理寻址方式进行操作，并提供从逻辑地址到物理地址的随机和顺序映射功能，同时支持大量逻辑地址空间之间的频繁上下文切换。本发明的实施例利用每个方向（源 - 目的地）排队和内部交换机来支持多个方向上数据的非阻塞并发传输。可以结合缓存技术来减少地址转换的开销。

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