专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08952519B2 Chip package and fabrication method thereof 有权
标题翻译：芯片封装及其制造方法
公开(公告)号：US08952519B2
公开(公告)日：2015-02-10
申请号：US12816301
申请日：2010-06-15
申请人： Chia-Sheng Lin , Po-Han Lee
发明人： Chia-Sheng Lin , Po-Han Lee
IPC分类号： H01L23/48 , H01L23/538 , H01L21/48 , H01L23/00
CPC分类号： H01L21/76898 , H01L21/481 , H01L21/76897 , H01L23/3178 , H01L23/3192 , H01L23/5389 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/19 , H01L24/94 , H01L27/14618 , H01L27/14636 , H01L2224/02372 , H01L2224/0345 , H01L2224/0401 , H01L2224/04026 , H01L2224/04105 , H01L2224/05548 , H01L2224/05567 , H01L2224/05624 , H01L2224/05639 , H01L2224/05647 , H01L2224/05655 , H01L2224/06181 , H01L2224/1132 , H01L2224/11462 , H01L2224/11849 , H01L2224/13022 , H01L2224/131 , H01L2224/20 , H01L2224/94 , H01L2224/97 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01047 , H01L2924/01075 , H01L2924/01079 , H01L2924/014 , H01L2924/12041 , H01L2924/14 , H01L2924/1461 , H01L2924/15787 , H01L2924/15788 , H01L2924/1579 , H01L2924/00
摘要： A chip package and a fabrication method thereof are provided. The chip package includes a semiconductor substrate, having a first surface and an opposing second surface. A spacer is disposed under the second surface of the semiconductor substrate and a cover plate is disposed under the spacer. A recessed portion is formed adjacent to a sidewall of the semiconductor substrate, extending from the first surface of the semiconductor substrate to at least the spacer. Then, a protection layer is disposed over the first surface of the semiconductor substrate and in the recessed portion.
摘要翻译：提供了芯片封装及其制造方法。芯片封装包括具有第一表面和相对的第二表面的半导体衬底。间隔件设置在半导体衬底的第二表面下方，并且覆盖板设置在间隔件下方。形成与半导体衬底的侧壁相邻的凹部，从半导体衬底的第一表面延伸到至少间隔件。然后，保护层设置在半导体衬底的第一表面和凹部中。

2. 发明申请

US20110169139A1 CHIP PACKAGE AND FABRICATION METHOD THEREOF 有权
标题翻译：芯片包装及其制造方法
公开(公告)号：US20110169139A1
公开(公告)日：2011-07-14
申请号：US12687093
申请日：2010-01-13
申请人： Chia-Sheng Lin , Chia-Lun Tsai , Chang-Sheng Hsu , Po-Han Lee
发明人： Chia-Sheng Lin , Chia-Lun Tsai , Chang-Sheng Hsu , Po-Han Lee
IPC分类号： H01L23/48 , H01L21/78
CPC分类号： H01L24/73 , H01L23/481 , H01L24/11 , H01L24/13 , H01L24/19 , H01L24/29 , H01L24/94 , H01L2224/0231 , H01L2224/0401 , H01L2224/05624 , H01L2224/05639 , H01L2224/05647 , H01L2224/05655 , H01L2224/13022 , H01L2924/01013 , H01L2924/01029 , H01L2924/01047 , H01L2924/01075 , H01L2924/014 , H01L2924/14 , H01L2924/1461 , H01L2924/3512 , H01L2924/00 , H01L2924/00014 , H01L2924/013
摘要： A chip package and a fabrication method thereof are provided. The chip package includes a semiconductor substrate, having a first surface and an opposite second surface. A through hole is formed on the first surface, extending from the first surface to the second surface. A conductive trace layer is formed on the first surface and in the through hole. A buffer plug is formed in the through hole and a protection layer is formed over the first surface and in the through hole.
摘要翻译：提供了芯片封装及其制造方法。芯片封装包括具有第一表面和相对的第二表面的半导体衬底。在第一表面上形成有从第一表面延伸到第二表面的通孔。导电迹线层形成在第一表面和通孔中。在通孔中形成缓冲塞，在第一表面和通孔中形成保护层。

3. 发明申请

US20090289345A1 ELECTRONIC DEVICE PACKAGE AND FABRICATION METHOD THEREOF 有权
标题翻译：电子器件封装及其制造方法
公开(公告)号：US20090289345A1
公开(公告)日：2009-11-26
申请号：US12470255
申请日：2009-05-21
申请人： Chia-Lun TSAI , Wen-Cheng CHIEN , Po-Han LEE , Wei-Ming CHEN
发明人： Chia-Lun TSAI , Wen-Cheng CHIEN , Po-Han LEE , Wei-Ming CHEN
IPC分类号： H01L23/48 , H01L21/00
CPC分类号： H01L23/481 , H01L21/76898 , H01L24/12 , H01L27/14618 , H01L27/14683 , H01L2224/05001 , H01L2224/05024 , H01L2224/05026 , H01L2224/05548 , H01L2224/05624 , H01L2224/05639 , H01L2224/05655 , H01L2924/00014 , H01L2924/01021 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/1461 , H01L2924/3025 , H01L2924/00 , H01L2224/05099
摘要： An electronic device package and a fabrication method thereof are provided. The fabrication method includes providing a semiconductor substrate containing a plurality of chips having a first surface and an opposite second surface. A plurality of conductive electrodes is disposed on the first surface and the conductive electrodes of the two adjacent chips are arranged asymmetrically along side direction of the chip. A plurality of contact holes is formed in each chip, apart from the side of the chip, to expose the conductive electrodes.
摘要翻译：提供一种电子器件封装及其制造方法。制造方法包括提供含有多个具有第一表面和相对的第二表面的芯片的半导体衬底。多个导电电极设置在第一表面上，并且两个相邻芯片的导电电极沿着芯片的侧面方向非对称地布置。在每个芯片中，与芯片侧面形成多个接触孔，以露出导电电极。

4. 发明申请

US20080303110A1 Integrated circuit package and method for operating and fabricating thereof 审中-公开
标题翻译：集成电路封装及其操作和制造方法
公开(公告)号：US20080303110A1
公开(公告)日：2008-12-11
申请号：US11892118
申请日：2007-08-20
申请人： Po-Han Lee
发明人： Po-Han Lee
IPC分类号： H01L31/0203 , H01L21/02
CPC分类号： H01L27/14618 , H01L27/1446 , H01L31/0203 , H01L2224/05001 , H01L2224/05023 , H01L2224/05124 , H01L2224/05147 , H01L2224/05184 , H01L2224/05568 , H01L2224/05647 , H01L2224/13 , H01L2924/00014
摘要： The invention provides an integrated circuit package and method for operating and fabricating thereof. The package comprises a transparent substrate having a first surface and a second surface opposite to each other and a semiconductor layer formed on the second surface of the transparent substrate. A photosensitive device is fabricated on the semiconductor layer and a metal plug is formed over the second surface of the transparent substrate and they are electrically connected to each other. A solder ball is formed over the second surface of the transparent substrate and electrically connected to the metal plug. In the package, the photosensitive device senses light penetrating the transparent substrate and the semiconductor layer through its backside to produce a signal which is subsequently transmitted to solder ball by the metal plug. Thus, the signal conductive path is shortened. Moreover, the photosensitive device is directly formed on the semiconductor layer without extra steps, for example bonding and notching, fabrication processes are reduced. Thus, fabrication cost is reduced.
摘要翻译：本发明提供一种用于其操作和制造的集成电路封装和方法。该封装包括具有彼此相对的第一表面和第二表面的透明基板和形成在透明基板的第二表面上的半导体层。在半导体层上制造感光装置，并且在透明基板的第二表面上形成金属插塞，并且它们彼此电连接。在透明基板的第二表面上形成焊球并电连接到金属插塞。在封装中，感光装置通过其背面感测穿透透明基板和半导体层的光，以产生随后通过金属插塞传输到焊球的信号。因此，信号导通路径被缩短。此外，感光装置直接形成在半导体层上，而没有额外的步骤，例如结合和切口，制造工艺减少。因此，制造成本降低。

5. 发明授权

US08319347B2 Electronic device package and fabrication method thereof 有权
标题翻译：电子器件封装及其制造方法
公开(公告)号：US08319347B2
公开(公告)日：2012-11-27
申请号：US12470255
申请日：2009-05-21
申请人： Chia-Lun Tsai , Wen-Cheng Chien , Po-Han Lee , Wei-Ming Chen
发明人： Chia-Lun Tsai , Wen-Cheng Chien , Po-Han Lee , Wei-Ming Chen
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L21/46 , H01L21/4763
CPC分类号： H01L23/481 , H01L21/76898 , H01L24/12 , H01L27/14618 , H01L27/14683 , H01L2224/05001 , H01L2224/05024 , H01L2224/05026 , H01L2224/05548 , H01L2224/05624 , H01L2224/05639 , H01L2224/05655 , H01L2924/00014 , H01L2924/01021 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/1461 , H01L2924/3025 , H01L2924/00 , H01L2224/05099
摘要： An electronic device package and a fabrication method thereof are provided. The fabrication method includes providing a semiconductor substrate containing a plurality of chips having a first surface and an opposite second surface. A plurality of conductive electrodes is disposed on the first surface and the conductive electrodes of the two adjacent chips are arranged asymmetrically along side direction of the chip. A plurality of contact holes is formed in each chip, apart from the side of the chip, to expose the conductive electrodes.
摘要翻译：提供一种电子器件封装及其制造方法。制造方法包括提供含有多个具有第一表面和相对的第二表面的芯片的半导体衬底。多个导电电极设置在第一表面上，并且两个相邻芯片的导电电极沿着芯片的侧面方向非对称地布置。在每个芯片中，与芯片侧面形成多个接触孔，以露出导电电极。

6. 发明申请

US20100201568A1 METHOD FOR IMPLEMENTING GPS SURVEYING FIELD WORK PLANNING USING 3D TOPOGRAPHIC INFORMAITON AND METHOD FOR ANALYZING 3D TOPOGRAPHIC INFORMATION 审中-公开
标题翻译：使用3D地形信息技术实现GPS测量现场工作规划的方法和分析3D地形信息的方法
公开(公告)号：US20100201568A1
公开(公告)日：2010-08-12
申请号：US12552859
申请日：2009-09-02
申请人： Jen-Yu Han , Po-Han Lee
发明人： Jen-Yu Han , Po-Han Lee
IPC分类号： G01S1/00
CPC分类号： G01S19/28 , G06T17/05
摘要： A method for implementing GPS surveying field work planning by using three dimensional topographic information is provided, comprising the steps of: obtaining three dimensional topographic information according to the location of a GPS receiver; obtaining maximum topographic elevation angle information from the GPS receiver to the terrain for each azimuth using the three dimension topographic information; obtaining elevation angle of satellites from the GPS receiver according to the satellite ephemeris or almanac; determining whether observation is usable according to the maximum topographic elevation angle information along the satellite bearings, and the elevation angle of satellites; and estimating the positioning accuracy according to the usable satellite observations.
摘要翻译：提供了一种通过使用三维地形信息实现GPS测量现场工作规划的方法，包括以下步骤：根据GPS接收机的位置获取三维地形信息; 使用三维地形信息，从GPS接收机获取每个方位的地形的最大地形仰角信息; 根据卫星星历或年历从GPS接收机获取卫星的仰角; 根据卫星轴承的最大地形仰角信息和卫星仰角确定观测是否可用; 并根据可用的卫星观测估计定位精度。

7. 发明申请

US20100187697A1 ELECTRONIC DEVICE PACKAGE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：电子设备包装及其制造方法
公开(公告)号：US20100187697A1
公开(公告)日：2010-07-29
申请号：US12667383
申请日：2008-06-13
申请人： Chia-Lun Tsai , Wen-Cheng Chien , Po-Han Lee , Wei-Ming Chen , Chien-Hung Liu , Ying-Nan Wen
发明人： Chia-Lun Tsai , Wen-Cheng Chien , Po-Han Lee , Wei-Ming Chen , Chien-Hung Liu , Ying-Nan Wen
IPC分类号： H01L23/528
CPC分类号： H01L23/481 , H01L21/76898 , H01L24/12 , H01L27/14618 , H01L27/14683 , H01L2224/05001 , H01L2224/05024 , H01L2224/05026 , H01L2224/05548 , H01L2224/05624 , H01L2224/05639 , H01L2224/05655 , H01L2924/00014 , H01L2924/01021 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/1461 , H01L2924/3025 , H01L2924/00 , H01L2224/05099
摘要： An embodiment of the present invention provides an electronic device package, which includes a chip having a first surface and an opposite second surface and a trench extending into a body of the chip along a direction from the second surface to the first surface, wherein a bottom portion of the trench includes at least two contact holes.
摘要翻译：本发明的实施例提供了一种电子器件封装，其包括具有第一表面和相对的第二表面的芯片以及沿着从第二表面到第一表面的方向延伸到芯片的主体中的沟槽，其中底部沟槽的一部分包括至少两个接触孔。

8. 发明授权

US08823179B2 Electronic device package and method for fabricating the same 有权
标题翻译：电子器件封装及其制造方法
公开(公告)号：US08823179B2
公开(公告)日：2014-09-02
申请号：US12667383
申请日：2008-06-13
申请人： Chia-Lun Tsai , Wen-Cheng Chien , Po-Han Lee , Wei-Ming Chen , Chien-Hung Liu , Ying-Nan Wen
发明人： Chia-Lun Tsai , Wen-Cheng Chien , Po-Han Lee , Wei-Ming Chen , Chien-Hung Liu , Ying-Nan Wen
IPC分类号： H01L23/48 , H01L27/146 , H01L21/768 , H01L23/00
CPC分类号： H01L23/481 , H01L21/76898 , H01L24/12 , H01L27/14618 , H01L27/14683 , H01L2224/05001 , H01L2224/05024 , H01L2224/05026 , H01L2224/05548 , H01L2224/05624 , H01L2224/05639 , H01L2224/05655 , H01L2924/00014 , H01L2924/01021 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/1461 , H01L2924/3025 , H01L2924/00 , H01L2224/05099
摘要： An embodiment of the present invention provides an electronic device package, which includes a chip having a first surface and an opposite second surface and a trench extending into a body of the chip along a direction from the second surface to the first surface, wherein a bottom portion of the trench includes at least two contact holes.
摘要翻译：本发明的实施例提供了一种电子器件封装，其包括具有第一表面和相对的第二表面的芯片以及沿着从第二表面到第一表面的方向延伸到芯片的主体中的沟槽，其中底部沟槽的一部分包括至少两个接触孔。

9. 发明授权

US08432032B2 Chip package and fabrication method thereof 有权
标题翻译：芯片封装及其制造方法
公开(公告)号：US08432032B2
公开(公告)日：2013-04-30
申请号：US12687093
申请日：2010-01-13
申请人： Chia-Sheng Lin , Chia-Lun Tsai , Chang-Sheng Hsu , Po-Han Lee
发明人： Chia-Sheng Lin , Chia-Lun Tsai , Chang-Sheng Hsu , Po-Han Lee
IPC分类号： H01L23/48
CPC分类号： H01L24/73 , H01L23/481 , H01L24/11 , H01L24/13 , H01L24/19 , H01L24/29 , H01L24/94 , H01L2224/0231 , H01L2224/0401 , H01L2224/05624 , H01L2224/05639 , H01L2224/05647 , H01L2224/05655 , H01L2224/13022 , H01L2924/01013 , H01L2924/01029 , H01L2924/01047 , H01L2924/01075 , H01L2924/014 , H01L2924/14 , H01L2924/1461 , H01L2924/3512 , H01L2924/00 , H01L2924/00014 , H01L2924/013
摘要： A chip package and a fabrication method thereof are provided. The chip package includes a semiconductor substrate, having a first surface and an opposite second surface. A through hole is formed on the first surface, extending from the first surface to the second surface. A conductive trace layer is formed on the first surface and in the through hole. A buffer plug is formed in the through hole and a protection layer is formed over the first surface and in the through hole.
摘要翻译：提供了芯片封装及其制造方法。芯片封装包括具有第一表面和相对的第二表面的半导体衬底。在第一表面上形成有从第一表面延伸到第二表面的通孔。导电迹线层形成在第一表面和通孔中。在通孔中形成缓冲塞，在第一表面和通孔中形成保护层。

10. 发明申请

US20110169159A1 CHIP PACKAGE AND FABRICATION METHOD THEREOF 有权
标题翻译：芯片包装及其制造方法
公开(公告)号：US20110169159A1
公开(公告)日：2011-07-14
申请号：US12816301
申请日：2010-06-15
申请人： Chia-Sheng LIN , Po-Han Lee
发明人： Chia-Sheng LIN , Po-Han Lee
IPC分类号： H01L23/48 , H01L21/78
CPC分类号： H01L21/76898 , H01L21/481 , H01L21/76897 , H01L23/3178 , H01L23/3192 , H01L23/5389 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/19 , H01L24/94 , H01L27/14618 , H01L27/14636 , H01L2224/02372 , H01L2224/0345 , H01L2224/0401 , H01L2224/04026 , H01L2224/04105 , H01L2224/05548 , H01L2224/05567 , H01L2224/05624 , H01L2224/05639 , H01L2224/05647 , H01L2224/05655 , H01L2224/06181 , H01L2224/1132 , H01L2224/11462 , H01L2224/11849 , H01L2224/13022 , H01L2224/131 , H01L2224/20 , H01L2224/94 , H01L2224/97 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01047 , H01L2924/01075 , H01L2924/01079 , H01L2924/014 , H01L2924/12041 , H01L2924/14 , H01L2924/1461 , H01L2924/15787 , H01L2924/15788 , H01L2924/1579 , H01L2924/00
摘要： A chip package and a fabrication method thereof are provided. The chip package includes a semiconductor substrate, having a first surface and an opposing second surface. A spacer is disposed under the second surface of the semiconductor substrate and a cover plate is disposed under the spacer. A recessed portion is formed adjacent to a sidewall of the semiconductor substrate, extending from the first surface of the semiconductor substrate to at least the spacer. Then, a protection layer is disposed over the first surface of the semiconductor substrate and in the recessed portion.
摘要翻译：提供了芯片封装及其制造方法。芯片封装包括具有第一表面和相对的第二表面的半导体衬底。间隔件设置在半导体衬底的第二表面下方，并且覆盖板设置在间隔件下方。形成与半导体衬底的侧壁相邻的凹部，从半导体衬底的第一表面延伸到至少间隔件。然后，保护层设置在半导体衬底的第一表面和凹部中。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式