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1. 发明申请

US20130021048A1 IC, CIRCUITRY, AND RF BIST SYSTEM 有权
标题翻译： IC，电路和RF BIST系统
公开(公告)号：US20130021048A1
公开(公告)日：2013-01-24
申请号：US13480969
申请日：2012-05-25
申请人： Chun-Hsien PENG , Pei-Wei CHEN , Ping-Hsuan TSU , ChiaYu YANG , Chun-Yu LIN
发明人： Chun-Hsien PENG , Pei-Wei CHEN , Ping-Hsuan TSU , ChiaYu YANG , Chun-Yu LIN
IPC分类号： G01R31/26
CPC分类号： G01R31/2822 , G01R31/2884
摘要： An IC, a circuitry, and an RF BIST system are provided. The RF BIST system includes a test equipment, a module circuitry, and an IC. The IC is arranged to communicate with the module circuitry by an RF signal in response to a command signal from the test equipment, determine a test result by the RF signal, and report the test result to the test equipment, wherein the module circuitry is external to the IC and the test equipment.
摘要翻译：提供IC，电路和RF BIST系统。 RF BIST系统包括测试设备，模块电路和IC。 IC被布置为响应于来自测试设备的命令信号通过RF信号与模块电路通信，通过RF信号确定测试结果，并将测试结果报告给测试设备，其中模块电路是外部的到IC和测试设备。

2. 发明申请

US20090195419A1 MEMORY CODE GENERATOR 有权
标题翻译：存储代码生成器
公开(公告)号：US20090195419A1
公开(公告)日：2009-08-06
申请号：US12203347
申请日：2008-09-03
申请人： Ping Hsuan Tsu , Chun-Nan Chen
发明人： Ping Hsuan Tsu , Chun-Nan Chen
IPC分类号： H03M7/00
CPC分类号： H04B1/7075 , G01S19/30 , G01S19/37 , H04B2201/70707 , H04B2201/70715
摘要： The invention provides a memory code generator. In one embodiment, the memory code generator comprises a code memory, a preparation buffer set, and a correlation buffer set. The code memory stores code data. The preparation buffer set retrieves a first code segment of the code data from the code memory, and shifts the first code segment to obtain a second code segment with a desired code phase required by the correlation buffer set. The correlation buffer set loads the second code segment from the preparation buffer set, and provides a correlation code for correlation according to the second code segment. The preparation buffer set prepares the second code segment corresponding to a subsequent correlation when the correlation buffer set is providing the correlation code for a current correlation according to the first code segment.
摘要翻译：本发明提供了一种存储器代码生成器。在一个实施例中，存储器代码生成器包括代码存储器，准备缓冲器组和相关缓冲器组。代码存储器存储代码数据。准备缓冲器组从代码存储器中检索代码数据的第一代码段，并移位第一代码段以获得具有相关缓冲器组所需的期望代码相位的第二代码段。相关缓冲器集合从准备缓冲器集合加载第二代码段，并根据第二代码段提供相关代码。当相关缓冲器组根据第一代码段为当前的相关提供相关代码时，准备缓冲器组准备对应于后续相关的第二代码段。

3. 发明授权

US09124345B2 If process engine and receiver having the same and method for removing if carriers used therein 有权
标题翻译：如果过程引擎和接收机具有相同的方法以及如何去除其中使用的载体的方法
公开(公告)号：US09124345B2
公开(公告)日：2015-09-01
申请号：US12326476
申请日：2008-12-02
申请人： Chun-nan Chen , Ping-hsuan Tsu
发明人： Chun-nan Chen , Ping-hsuan Tsu
IPC分类号： H04B1/26 , H04B1/30 , H04B1/00
CPC分类号： H04B1/30 , H04B1/0007 , H04B1/005 , H04B1/006 , H04B1/0067
摘要： A GNSS receiver having an IF process engine is disclosed. The IF process engine provides a plurality of carriers with different frequencies and down converts IF signals into baseband signals by using the carriers in a time division multiplex (TDM) schedule. The IF process engine has a local oscillator part for generating the carriers with different frequencies; an IF down-converter for respectively mixing the IF signal with the carriers generated by the local oscillator part to generate IF removed signal segments; a time division multiplex (TDM) controller for scheduling the respective mixing operations of the IF down-converter for the IF signal with the respective carriers; and a buffer for storing the IF removed signal segments generated by the IF down-converter.
摘要翻译：公开了具有IF处理引擎的GNSS接收机。 IF处理引擎提供具有不同频率的多个载波，并且通过使用时分复用（TDM）调度中的载波，将IF信号下变频为基带信号。 IF处理引擎具有用于生成具有不同频率的载波的本地振荡器部分; 用于分别将IF信号与由本地振荡器部分产生的载波混合以产生IF去除的信号段的IF下变频器; 时分复用（TDM）控制器，用于调度具有各个载波的IF信号的IF下变频器的各自的混合操作; 以及用于存储由IF下变频器产生的IF去除的信号段的缓冲器。

4. 发明申请

US20090081978A1 IF PROCESS ENGINE AND RECEIVER HAVING THE SAME AND METHOD FOR REMOVING IF CARRIERS USED THEREIN 有权
标题翻译：如果具有相同的过程发动机和接收器以及如果使用其中的载波移除方法
公开(公告)号：US20090081978A1
公开(公告)日：2009-03-26
申请号：US12326476
申请日：2008-12-02
申请人： Chun-nan Chen , Ping-hsuan Tsu
发明人： Chun-nan Chen , Ping-hsuan Tsu
IPC分类号： H04B1/06
CPC分类号： H04B1/30 , H04B1/0007 , H04B1/005 , H04B1/006 , H04B1/0067
摘要： A GNSS receiver having an IF process engine is disclosed. The IF process engine provides a plurality of carriers with different frequencies and down converts IF signals into baseband signals by using the carriers in a time division multiplex (TDM) schedule. The IF process engine has a local oscillator part for generating the carriers with different frequencies; an IF down-converter for respectively mixing the IF signal with the carriers generated by the local oscillator part to generate IF removed signal segments; a time division multiplex (TDM) controller for scheduling the respective mixing operations of the IF down-converter for the IF signal with the respective carriers; and a buffer for storing the IF removed signal segments generated by the IF down-converter.
摘要翻译：公开了具有IF处理引擎的GNSS接收机。 IF处理引擎提供具有不同频率的多个载波，并且通过使用时分复用（TDM）调度中的载波，将IF信号下变频为基带信号。 IF处理引擎具有用于生成具有不同频率的载波的本地振荡器部分; 用于分别将IF信号与由本地振荡器部分产生的载波混合以产生IF去除的信号段的IF下变频器; 时分复用（TDM）控制器，用于调度具有各个载波的IF信号的IF下变频器的各自的混合操作; 以及用于存储由IF下变频器产生的IF去除的信号段的缓冲器。

5. 发明授权

US09041421B2 IC, circuitry, and RF BIST system 有权
标题翻译： IC，电路和RF BIST系统
公开(公告)号：US09041421B2
公开(公告)日：2015-05-26
申请号：US13480969
申请日：2012-05-25
申请人： Chun-Hsien Peng , Pei-Wei Chen , Ping-Hsuan Tsu , ChiaYu Yang , Chun-Yu Lin
发明人： Chun-Hsien Peng , Pei-Wei Chen , Ping-Hsuan Tsu , ChiaYu Yang , Chun-Yu Lin
IPC分类号： G01R31/28
CPC分类号： G01R31/2822 , G01R31/2884
摘要： An IC, a circuitry, and an RF BIST system are provided. The RF BIST system includes a test equipment, a module circuitry, and an IC. The IC is arranged to communicate with the module circuitry by an RF signal in response to a command signal from the test equipment, determine a test result by the RF signal, and report the test result to the test equipment, wherein the module circuitry is external to the IC and the test equipment.
摘要翻译：提供IC，电路和RF BIST系统。 RF BIST系统包括测试设备，模块电路和IC。 IC被布置为响应于来自测试设备的命令信号通过RF信号与模块电路通信，通过RF信号确定测试结果，并将测试结果报告给测试设备，其中模块电路是外部的到IC和测试设备。

6. 发明授权

US08185718B2 Code memory capable of code provision for a plurality of physical channels 有权
标题翻译：能够为多个物理信道提供代码的代码存储器
公开(公告)号：US08185718B2
公开(公告)日：2012-05-22
申请号：US12203326
申请日：2008-09-03
申请人： Chun-Nan Chen , Ping Hsuan Tsu
发明人： Chun-Nan Chen , Ping Hsuan Tsu
IPC分类号： G06F12/00
CPC分类号： G01S19/37 , G01S19/30 , H04J13/10 , H04J13/16
摘要： The invention provides a code memory capable of code provision for a plurality of physical channels. In one embodiment, the code memory comprises a selecting multiplexer, a core memory module, and a code buffer. The selecting multiplexer repeatedly latches on to a plurality of addresses generated by the physical channels according to a sequence of the physical channels to generate a code memory address signal. The core memory module stores code data, and retrieves the code data according to the code memory address signal to generate a code memory data signal. The code buffer respectively retrieves a plurality of code segments requested by the physical channels from the code memory data signal according to the sequence of the physical channels, and stores the code segments.
摘要翻译：本发明提供了能够为多个物理信道提供代码的代码存储器。在一个实施例中，代码存储器包括选择多路复用器，核心存储器模块和代码缓冲器。选择多路复用器根据物理信道的序列重复锁存由物理信道生成的多个地址，以产生代码存储器地址信号。核心存储器模块存储代码数据，并且根据代码存储器地址信号检索代码数据，以产生代码存储器数据信号。代码缓冲器根据物理信道的顺序分别从代码存储器数据信号中检索由物理信道请求的多个代码段，并存储代码段。

7. 发明授权

US07667627B2 Memory code generator 有权
标题翻译：内存代码生成器
公开(公告)号：US07667627B2
公开(公告)日：2010-02-23
申请号：US12203347
申请日：2008-09-03
申请人： Ping Hsuan Tsu , Chun-Nan Chen
发明人： Ping Hsuan Tsu , Chun-Nan Chen
IPC分类号： H03M7/12
CPC分类号： H04B1/7075 , G01S19/30 , G01S19/37 , H04B2201/70707 , H04B2201/70715
摘要： The invention provides a memory code generator. In one embodiment, the memory code generator comprises a code memory, a preparation buffer set, and a correlation buffer set. The code memory stores code data. The preparation buffer set retrieves a first code segment of the code data from the code memory, and shifts the first code segment to obtain a second code segment with a desired code phase required by the correlation buffer set. The correlation buffer set loads the second code segment from the preparation buffer set, and provides a correlation code for correlation according to the second code segment. The preparation buffer set prepares the second code segment corresponding to a subsequent correlation when the correlation buffer set is providing the correlation code for a current correlation according to the first code segment.
摘要翻译：本发明提供了一种存储器代码生成器。在一个实施例中，存储器代码生成器包括代码存储器，准备缓冲器组和相关缓冲器组。代码存储器存储代码数据。准备缓冲器组从代码存储器中检索代码数据的第一代码段，并移位第一代码段以获得具有相关缓冲器组所需的期望代码相位的第二代码段。相关缓冲器集合从准备缓冲器集合加载第二代码段，并根据第二代码段提供相关代码。当相关缓冲器组根据第一代码段为当前的相关提供相关代码时，准备缓冲器组准备对应于后续相关的第二代码段。

8. 发明申请

US20090198866A1 CODE MEMORY CAPABLE OF CODE PROVISION FOR A PLURALITY OF PHYSICAL CHANNELS 有权
标题翻译：能够为多种物理通道提供规则的代码记录
公开(公告)号：US20090198866A1
公开(公告)日：2009-08-06
申请号：US12203326
申请日：2008-09-03
申请人： Chun-Nan CHEN , Ping Hsuan TSU
发明人： Chun-Nan CHEN , Ping Hsuan TSU
IPC分类号： G06F12/06
CPC分类号： G01S19/37 , G01S19/30 , H04J13/10 , H04J13/16
摘要： The invention provides a code memory capable of code provision for a plurality of physical channels. In one embodiment, the code memory comprises a selecting multiplexer, a core memory module, and a code buffer. The selecting multiplexer repeatedly latches on to a plurality of addresses generated by the physical channels according to a sequence of the physical channels to generate a code memory address signal. The core memory module stores code data, and retrieves the code data according to the code memory address signal to generate a code memory data signal. The code buffer respectively retrieves a plurality of code segments requested by the physical channels from the code memory data signal according to the sequence of the physical channels, and stores the code segments.
摘要翻译：本发明提供了能够为多个物理信道提供代码的代码存储器。在一个实施例中，代码存储器包括选择多路复用器，核心存储器模块和代码缓冲器。选择多路复用器根据物理信道的序列重复锁存由物理信道生成的多个地址，以产生代码存储器地址信号。核心存储器模块存储代码数据，并且根据代码存储器地址信号检索代码数据，以产生代码存储器数据信号。代码缓冲器根据物理信道的顺序分别从代码存储器数据信号中检索由物理信道请求的多个代码段，并存储代码段。

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