专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20110213998A1 System and Method for Power Optimization 审中-公开
标题翻译：功率优化的系统和方法
公开(公告)号：US20110213998A1
公开(公告)日：2011-09-01
申请号：US12787361
申请日：2010-05-25
申请人： John George Mathieson , Phil Carmack , Brian Smith
发明人： John George Mathieson , Phil Carmack , Brian Smith
IPC分类号： G06F1/32 , G06F15/76
CPC分类号： G06F1/3203 , G06F1/206 , G06F1/3237 , G06F1/324 , G06F1/3287 , G06F1/329 , G06F1/3293 , G06F9/5094 , G06F15/8007 , Y02D10/122 , Y02D10/126 , Y02D10/128 , Y02D10/16 , Y02D10/171 , Y02D10/22 , Y02D10/24
摘要： A technique for reducing the power consumption required to execute processing operations. A processing complex, such as a CPU or a GPU, includes a first set of cores comprising one or more fast cores and second set of cores comprising one or more slow cores. A processing mode of the processing complex can switch between a first mode of operation and a second mode of operation based on one or more of the workload characteristics, performance characteristics of the first and second sets of cores, power characteristics of the first and second sets of cores, and operating conditions of the processing complex. A controller causes the processing operations to be executed by either the first set of cores or the second set of cores to achieve the lowest total power consumption.
摘要翻译：用于降低执行处理操作所需功耗的技术。诸如CPU或GPU的处理复合体包括包括一个或多个快速核心的第一组核心和包括一个或多个慢核心的第二组核心。处理复合体的处理模式可以基于工作负载特性，第一和第二组核心的性能特征，第一和第二组的功率特性中的一个或多个来在第一操作模式和第二操作模式之间切换的核心，以及处理复杂的操作条件。控制器使处理操作由第一组核心或第二组核心执行，以实现最低的总功耗。

2. 发明申请

US20120331319A1 SYSTEM AND METHOD FOR POWER OPTIMIZATION 审中-公开
公开(公告)号：US20120331319A1
公开(公告)日：2012-12-27
申请号：US13604496
申请日：2012-09-05
申请人： John George Mathieson , Phil Carmack , Brian Smith
发明人： John George Mathieson , Phil Carmack , Brian Smith
IPC分类号： G06F1/32 , G06F12/08 , G06F9/30
CPC分类号： G06F9/5094 , G06F1/206 , G06F1/3203 , G06F1/324 , G06F1/3287 , G06F1/3293 , G06F9/5088 , G06F15/8007 , G06F2209/508 , Y02D10/122 , Y02D10/126 , Y02D10/16 , Y02D10/171 , Y02D10/22 , Y02D10/32
摘要： A technique for reducing the power consumption required to execute processing operations. A processing complex, such as a CPU or a GPU, includes a first set of cores comprising one or more fast cores and second set of cores comprising one or more slow cores. A processing mode of the processing complex can switch between a first mode of operation and a second mode of operation based on one or more of the workload characteristics, performance characteristics of the first and second sets of cores, power characteristics of the first and second sets of cores, and operating conditions of the processing complex. A controller causes the processing operations to be executed by either the first set of cores or the second set of cores to achieve the lowest total power consumption.

3. 发明申请

US20110213950A1 System and Method for Power Optimization 审中-公开
公开(公告)号：US20110213950A1
公开(公告)日：2011-09-01
申请号：US12787359
申请日：2010-05-25
申请人： John George Mathieson , Phil Carmack , Brian Smith
发明人： John George Mathieson , Phil Carmack , Brian Smith
IPC分类号： G06F15/76 , G06F9/02
CPC分类号： G06F9/5094 , G06F1/206 , G06F1/3203 , G06F1/324 , G06F1/3287 , G06F1/329 , G06F1/3293 , G06F9/5088 , G06F15/8007 , G06F2209/5022 , G06F2209/508 , Y02D10/122 , Y02D10/126 , Y02D10/16 , Y02D10/171 , Y02D10/22 , Y02D10/24 , Y02D10/32
摘要： A technique for reducing the power consumption required to execute processing operations. A processing complex, such as a CPU or a GPU, includes a first set of cores comprising one or more fast cores and second set of cores comprising one or more slow cores. A processing mode of the processing complex can switch between a first mode of operation and a second mode of operation based on one or more of the workload characteristics, performance characteristics of the first and second sets of cores, power characteristics of the first and second sets of cores, and operating conditions of the processing complex. A controller causes the processing operations to be executed by either the first set of cores or the second set of cores to achieve the lowest total power consumption.

4. 发明申请

US20120331275A1 SYSTEM AND METHOD FOR POWER OPTIMIZATION 审中-公开
标题翻译：电力优化的系统和方法
公开(公告)号：US20120331275A1
公开(公告)日：2012-12-27
申请号：US13604390
申请日：2012-09-05
申请人： John George Mathieson , Phil Carmack , Brian Smith
发明人： John George Mathieson , Phil Carmack , Brian Smith
IPC分类号： G06F9/318
CPC分类号： G06F1/3203 , G06F1/206 , G06F1/3237 , G06F1/324 , G06F1/3287 , G06F1/329 , G06F1/3293 , G06F9/5094 , G06F15/8007 , Y02D10/122 , Y02D10/126 , Y02D10/128 , Y02D10/16 , Y02D10/171 , Y02D10/22 , Y02D10/24
摘要： A technique for reducing the power consumption required to execute processing operations. A processing complex, such as a CPU or a GPU, includes a first set of cores comprising one or more fast cores and second set of cores comprising one or more slow cores. A processing mode of the processing complex can switch between a first mode of operation and a second mode of operation based on one or more of the workload characteristics, performance characteristics of the first and second sets of cores, power characteristics of the first and second sets of cores, and operating conditions of the processing complex. A controller causes the processing operations to be executed by either the first set of cores or the second set of cores to achieve the lowest total power consumption.
摘要翻译：用于降低执行处理操作所需功耗的技术。诸如CPU或GPU的处理复合体包括包括一个或多个快速核心的第一组核心和包括一个或多个慢核心的第二组核心。处理复合体的处理模式可以基于工作负荷特性，第一和第二组核心的性能特征，第一和第二组的功率特性中的一个或多个来在第一操作模式和第二操作模式之间切换的核心，以及处理复杂的操作条件。控制器使处理操作由第一组核心或第二组核心执行，以实现最低的总功耗。

5. 发明申请

US20110213947A1 System and Method for Power Optimization 审中-公开
公开(公告)号：US20110213947A1
公开(公告)日：2011-09-01
申请号：US12787360
申请日：2010-05-25
申请人： John George Mathieson , Phil Carmack , Brian Smith
发明人： John George Mathieson , Phil Carmack , Brian Smith
IPC分类号： G06F9/44 , G06F15/76 , G06F12/08
CPC分类号： G06F9/5094 , G06F1/206 , G06F1/3203 , G06F1/324 , G06F1/3287 , G06F1/3293 , G06F9/5088 , G06F15/8007 , G06F2209/508 , Y02D10/122 , Y02D10/126 , Y02D10/16 , Y02D10/171 , Y02D10/22 , Y02D10/32
摘要： A technique for reducing the power consumption required to execute processing operations. A processing complex, such as a CPU or a GPU, includes a first set of cores comprising one or more fast cores and second set of cores comprising one or more slow cores. A processing mode of the processing complex can switch between a first mode of operation and a second mode of operation based on one or more of the workload characteristics, performance characteristics of the first and second sets of cores, power characteristics of the first and second sets of cores, and operating conditions of the processing complex. A controller causes the processing operations to be executed by either the first set of cores or the second set of cores to achieve the lowest total power consumption.

6. 发明申请

US20090309243A1 MULTI-CORE INTEGRATED CIRCUITS HAVING ASYMMETRIC PERFORMANCE BETWEEN CORES 审中-公开
标题翻译：具有不相关性能的多核集成电路
公开(公告)号：US20090309243A1
公开(公告)日：2009-12-17
申请号：US12137053
申请日：2008-06-11
申请人： Phil Carmack , Brian Smith
发明人： Phil Carmack , Brian Smith
IPC分类号： H01L23/58
CPC分类号： G06F15/8007 , G06F1/206 , G06F1/3203 , G06F1/3287 , G06F1/3293 , Y02D10/122 , Y02D10/126 , Y02D10/16 , Y02D10/171
摘要： An integrated circuit in one embodiment includes asymmetric cores and an asymmetric core control circuit. At least one of the asymmetric cores is a different implementation of substantially the same function or subset of functionality as another core. The asymmetric core control circuit determines a performance parameter of an integrated circuit. The performance parameter may be the workload, the operating frequency, power consumption, quality of service, operating temperature or the like of the integrated circuit or a given portion of the integrated circuit. If the performance parameter is within a first range, the asymmetric core control circuit utilizes a first core to perform a function of the integrated circuit and idles a second core that is a different implementation of substantially the same function. If the performance parameter is within a second range, the core control circuit utilizes the second core to perform the function and idles the first core.
摘要翻译：在一个实施例中的集成电路包括不对称核心和不对称核心控制电路。不对称核心中的至少一个是与另一核心基本上相同的功能或功能子集的不同实现。非对称核心控制电路确定集成电路的性能参数。性能参数可以是集成电路或集成电路的给定部分的工作负载，工作频率，功耗，服务质量，工作温度等。如果性能参数在第一范围内，则不对称核心控制电路利用第一核来执行集成电路的功能，并且空闲第二核心，该第二核心是基本上相同功能的不同实现。如果性能参数在第二范围内，则核心控制电路利用第二核来执行功能并使第一核心空闲。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式