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1. 发明授权

US09178815B2 NIC flow switching 有权
标题翻译：网卡流量切换
公开(公告)号：US09178815B2
公开(公告)日：2015-11-03
申请号：US13785693
申请日：2013-03-05
申请人： Iosif Gasparakis , Peter P. Waskiewicz , Patrick Connor
发明人： Iosif Gasparakis , Peter P. Waskiewicz , Patrick Connor
IPC分类号： H04L29/06 , H04L12/741 , H04L12/28 , H04L12/56
CPC分类号： H04L45/74 , H04L47/50 , H04L61/6022 , H04L69/12 , H04L69/324
摘要： Methods, apparatus, and systems for implementing in Network Interface Controller (NIC) flow switching. Switching operations are effected via hardware-based forwarding mechanisms in apparatus such as NICs in a manner that does not employ use of computer system processor resources and is transparent to operating systems hosted by such computer systems. The forwarding mechanisms are configured to move or copy Media Access Control (MAC) frame data between receive (Rx) and transmit (Tx) queues associated with different NIC ports that may be on the same NIC or separate NICs. The hardware-based switching operations effect forwarding of MAC frames between NIC ports using memory operations, thus reducing external network traffic, internal interconnect traffic, and processor workload associated with packet processing.
摘要翻译：在网络接口控制器（NIC）流切换中实现的方法，设备和系统。切换操作通过诸如NIC的设备中的基于硬件的转发机制以不使用计算机系统处理器资源的方式实现，并且对由这样的计算机系统托管的操作系统是透明的。转发机制被配置为在与可能在同一NIC或单独NIC上的不同NIC端口相关联的接收（Rx）和发送（Tx）队列之间移动或复制媒体访问控制（MAC）帧数据。基于硬件的交换操作通过存储器操作来影响NIC端口之间的MAC帧的转发，从而减少与分组处理相关联的外部网络流量，内部互连流量和处理器工作量。

2. 发明申请

US20130318334A1 DYNAMIC INTERRUPT RECONFIGURATION FOR EFFECTIVE POWER MANAGEMENT 审中-公开
标题翻译：动态中断重新配置有效的电源管理
公开(公告)号：US20130318334A1
公开(公告)日：2013-11-28
申请号：US13977605
申请日：2012-04-24
申请人： Peter P. Waskiewicz, JR.
发明人： Peter P. Waskiewicz, JR.
IPC分类号： G06F9/38
CPC分类号： G06F9/3861 , G06F1/3203 , G06F1/329 , G06F9/4812 , G06F13/24 , Y02D10/24
摘要： Methods, apparatus, and systems for facilitating effective power management through dynamic reconfiguration of interrupts. Interrupt vectors are mapped to various processor cores in a multi-core processor, and interrupt workloads on the processor cores are monitored. When an interrupt workload for a given processor core is detected to fall below a threshold, the interrupt vectors are dynamically reconfigured by remapping interrupt vectors that are currently mapped to the processor core to at least one other processor core, such that there are no interrupt vectors mapped to the processor core after reconfiguration. The core is then enabled to be put in a deeper idle state. Similar operations can be applied to additional processor cores, effecting a collapsing of interrupt vectors onto fewer processor cores. In response to detecting cores emerging from idle states, reconfiguration of interrupt vectors can be performed to rebalance the assignment of the vectors across active cores by remapping a portion of the vectors to those cores.
摘要翻译：用于通过动态重新配置中断来促进有效电源管理的方法，装置和系统。中断向量映射到多核处理器中的各种处理器内核，并监视处理器内核上的中断工作负载。当检测到给定处理器核心的中断工作负载低于阈值时，通过将当前映射到处理器核心的中断向量重新映射到至少一个其他处理器核心，中断向量被动态重新配置，使得不存在中断向量重新配置后映射到处理器核心。然后核心能够被置于更深的空闲状态。类似的操作可以应用于附加的处理器内核，从而将中断向量折叠到较少的处理器内核上。响应于检测到从空闲状态出现的核心，可以执行重新配置中断向量，以通过将一部分向量重新映射到这些核来重新平衡跨活动核心的向量分配。

3. 发明授权

US09411725B2 Application-reserved cache for direct I/O 有权
标题翻译：用于直接I / O的应用保留缓存
公开(公告)号：US09411725B2
公开(公告)日：2016-08-09
申请号：US13993620
申请日：2012-03-22
申请人： Iosif Gasparakis , Peter P. Waskiewicz, Jr.
发明人： Iosif Gasparakis , Peter P. Waskiewicz, Jr.
IPC分类号： G06F12/08 , G06F9/50
CPC分类号： G06F12/0802 , G06F9/5016 , G06F2209/5014
摘要： Described are embodiments of mediums, methods, and systems for application-reserved use of cache for direct I/O. A method for using application-reserved cache may include reserving, by one of a plurality of cores of a processor, use of a first portion of one of a plurality of levels of cache for an application executed by the one of the plurality of cores, and transferring, by the one of the plurality of cores, data associated with the application from an input/output (I/O) device of a computing device directly to the first portion of the one of the plurality of levels of the cache. Other embodiments may be described and claimed.
摘要翻译：描述了用于直接I / O的缓存的应用保留使用的介质，方法和系统的实施例。一种使用应用预留高速缓存的方法可以包括：由多个核心中的一个核心执行的应用程序使用多个级别的高速缓存中的一个级别的第一部分，并且由多个核心中的一个核心将与应用程序相关联的数据从计算设备的输入/输出（I / O）设备直接传送到高速缓存的多个级别之一的第一部分。可以描述和要求保护其他实施例。

4. 发明申请

US20140254594A1 IN NIC FLOW SWITCHING 有权
标题翻译：在网卡流量开关
公开(公告)号：US20140254594A1
公开(公告)日：2014-09-11
申请号：US13785693
申请日：2013-03-05
申请人： Iosif Gasparakis , Peter P. Waskiewicz , Patrick Connor
发明人： Iosif Gasparakis , Peter P. Waskiewicz , Patrick Connor
IPC分类号： H04L12/56
CPC分类号： H04L45/74 , H04L47/50 , H04L61/6022 , H04L69/12 , H04L69/324
摘要： Methods, apparatus, and systems for implementing in Network Interface Controller (NIC) flow switching. Switching operations are effected via hardware-based forwarding mechanisms in apparatus such as NICs in a manner that does not employ use of computer system processor resources and is transparent to operating systems hosted by such computer systems. The forwarding mechanisms are configured to move or copy Media Access Control (MAC) frame data between receive (Rx) and transmit (Tx) queues associated with different NIC ports that may be on the same NIC or separate NICs. The hardware-based switching operations effect forwarding of MAC frames between NIC ports using memory operations, thus reducing external network traffic, internal interconnect traffic, and processor workload associated with packet processing.
摘要翻译：在网络接口控制器（NIC）流切换中实现的方法，设备和系统。切换操作通过诸如NIC的设备中的基于硬件的转发机制以不使用计算机系统处理器资源的方式实现，并且对由这样的计算机系统托管的操作系统是透明的。转发机制被配置为在与可能在同一NIC或单独NIC上的不同NIC端口相关联的接收（Rx）和发送（Tx）队列之间移动或复制媒体访问控制（MAC）帧数据。基于硬件的交换操作通过存储器操作来影响NIC端口之间的MAC帧的转发，从而减少与分组处理相关联的外部网络流量，内部互连流量和处理器工作量。

5. 发明申请

US20140059225A1 NETWORK CONTROLLER FOR REMOTE SYSTEM MANAGEMENT 审中-公开
标题翻译：远程系统管理网络控制器
公开(公告)号：US20140059225A1
公开(公告)日：2014-02-27
申请号：US13590631
申请日：2012-08-21
申请人： Iosif Gasparakis , Ilango S. Ganga , Peter P. Waskiewicz, JR.
发明人： Iosif Gasparakis , Ilango S. Ganga , Peter P. Waskiewicz, JR.
IPC分类号： H04L29/08
CPC分类号： H04L29/0818 , H04L41/0816 , H04L43/0829 , H04L43/0888
摘要： Generally, this disclosure describes a network controller for remote system management. A host device may include the network controller and a programmable network element. The network controller may include controller circuitry configured to acquire network management data related to operation of the network controller and to receive host management data related to operation of the host device. The network controller may further include a transmitter configured to transmit the network and host management data to a management system remote from the network controller and a receiver configured to receive a command from the management system related to the management data, the command configured to reprogram the programmable network element to change a behavior of the programmable network element.
摘要翻译：通常，本公开描述了用于远程系统管理的网络控制器。主机设备可以包括网络控制器和可编程网元。网络控制器可以包括被配置为获取与网络控制器的操作相关的网络管理数据并且接收与主机设备的操作有关的主机管理数据的控制器电路。网络控制器还可以包括发射机，被配置为将网络和主机管理数据发送到远离网络控制器的管理系统，以及被配置为从管理系统接收与管理数据有关的命令的接收机，该命令被配置为重新编程可编程网元改变可编程网元的行为。

6. 发明授权

US10990407B2 Dynamic interrupt reconfiguration for effective power management 有权
公开(公告)号：US10990407B2
公开(公告)日：2021-04-27
申请号：US13977605
申请日：2012-04-24
申请人： Peter P. Waskiewicz, Jr.
发明人： Peter P. Waskiewicz, Jr.
IPC分类号： G06F9/38 , G06F13/24 , G06F1/3203 , G06F1/329 , G06F9/48
摘要： Methods, apparatus, and systems for facilitating effective power management through dynamic reconfiguration of interrupts. Interrupt vectors are mapped to various processor cores in a multi-core processor, and interrupt workloads on the processor cores are monitored. When an interrupt workload for a given processor core is detected to fall below a threshold, the interrupt vectors are dynamically reconfigured by remapping interrupt vectors that are currently mapped to the processor core to at least one other processor core, such that there are no interrupt vectors mapped to the processor core after reconfiguration. The core is then enabled to be put in a deeper idle state. Similar operations can be applied to additional processor cores, effecting a collapsing of interrupt vectors onto fewer processor cores. In response to detecting cores emerging from idle states, reconfiguration of interrupt vectors can be performed to rebalance the assignment of the vectors across active cores by remapping a portion of the vectors to those cores.

7. 发明申请

US20140059170A1 PACKET PROCESSING OF DATA USING MULTIPLE MEDIA ACCESS CONTROLLERS 审中-公开
标题翻译：使用多媒体访问控制器的数据分组处理
公开(公告)号：US20140059170A1
公开(公告)日：2014-02-27
申请号：US13976460
申请日：2012-05-02
申请人： Iosif Gasparakis , Peter P. Waskiewicz, JR. , Ilango S. Ganga , Terry V. Hulett , Parathasarathy Sarangam
发明人： Iosif Gasparakis , Peter P. Waskiewicz, JR. , Ilango S. Ganga , Terry V. Hulett , Parathasarathy Sarangam
IPC分类号： H04L29/08
CPC分类号： H04L67/02 , G06F9/45533 , H04L69/321
摘要： Examples are disclosed for a device having at least two media access controllers. In some examples, a first media access controller may be coupled to a host computing device. A second media access controller may be coupled to one or more processor circuits arranged to perform packet processing of data payloads for one or more data frames forwarded through the first media access controller and/or forwarded through the second media access controller. The first media access controller may be coupled to the second media access controller via a communication link. Other examples are described and claimed.
摘要翻译：公开了具有至少两个媒体访问控制器的设备的示例。在一些示例中，第一媒体访问控制器可以耦合到主计算设备。第二媒体接入控制器可以耦合到一个或多个处理器电路，其被布置为对通过第一媒体接入控制器转发的一个或多个数据帧执行数据有效载荷的分组处理和/或通过第二媒体接入控制器转发。第一媒体接入控制器可以经由通信链路耦合到第二媒体接入控制器。其他的例子被描述和要求保护。

8. 发明申请

US20130318303A1 APPLICATION-RESERVED CACHE FOR DIRECT I/O 有权
标题翻译：用于直接I / O的应用保留缓存
公开(公告)号：US20130318303A1
公开(公告)日：2013-11-28
申请号：US13993620
申请日：2012-03-22
申请人： Iosif Gasparakis , Peter P. Waskiewicz, JR.
发明人： Iosif Gasparakis , Peter P. Waskiewicz, JR.
IPC分类号： G06F12/08
CPC分类号： G06F12/0802 , G06F9/5016 , G06F2209/5014
摘要： Described are embodiments of mediums, methods, and systems for application-reserved use of cache for direct I/O. A method for using application-reserved cache may include reserving, by one of a plurality of cores of a processor, use of a first portion of one of a plurality of levels of cache for an application executed by the one of the plurality of cores, and transferring, by the one of the plurality of cores, data associated with the application from an input/output (I/O) device of a computing device directly to the first portion of the one of the plurality of levels of the cache. Other embodiments may be described and claimed.
摘要翻译：描述了用于直接I / O的缓存的应用保留使用的介质，方法和系统的实施例。一种使用应用预留高速缓存的方法可以包括：由多个核心中的一个核心执行的应用程序使用多个级别的高速缓存中的一个级别的第一部分，并且由多个核心中的一个核心将与应用程序相关联的数据从计算设备的输入/输出（I / O）设备直接传送到高速缓存的多个级别之一的第一部分。可以描述和要求保护其他实施例。

9. 发明授权

US09112602B2 Method of automatically determining link speed for a multispeed fiber link module 有权
标题翻译：自动确定多速光纤链路模块链路速度的方法
公开(公告)号：US09112602B2
公开(公告)日：2015-08-18
申请号：US12823882
申请日：2010-06-25
申请人： Aaron K. Salter , Peter P. Waskiewicz, Jr. , Scott P. Dubal , Brian Kantor
发明人： Aaron K. Salter , Peter P. Waskiewicz, Jr. , Scott P. Dubal , Brian Kantor
IPC分类号： H04B10/073 , G06F15/16
CPC分类号： H04B10/0731
摘要： Automatically determining a link speed between link partners using a multispeed fiber module. An embodiment solves the problem of how to determine the highest common link speed between short range (SR)/long range (LR) fiber link partners when at least one of the link partners is using a multispeed fiber module. In an embodiment, a multispeed fiber module comprises a module that is capable of both 10 gigabit (GB) per second Ethernet and 1 GB per second Ethernet or lesser data transfer speeds over a fiber optical link. In an embodiment, the method comprises trying each link speed in a known succession, from highest supported speed to lowest supported speed. In an embodiment, an initiator link partner “blinks” a transmit laser, which alerts the link partners that a link speed determination session is being initiated. By automatically determining link speed, the user is relieved of the necessity to manually configure the link speed.
摘要翻译：使用多速光纤模块自动确定链路伙伴之间的链路速度。一个实施例解决了当至少一个链路伙伴使用多速光纤模块时如何确定短距离（SR）/远程（LR）光纤链路伙伴之间的最高公共链路速度的问题。在一个实施例中，多速光纤模块包括能够每秒10吉比特（GB）以太网和1GB /秒以太网或光纤光链路上的较小数据传输速度的模块。在一个实施例中，该方法包括以已知连续的方式尝试每个链路速度，从最高支持速度到最低支持速度。在一个实施例中，发起者链路伙伴“闪烁”发射激光器，其向链路伙伴通知正在启动链路速度确定会话。通过自动确定链路速度，用户不需要手动配置链路速度。

10. 发明授权

US08555368B2 Firewall filtering using network controller circuitry 有权
标题翻译：使用网络控制器电路的防火墙过滤
公开(公告)号：US08555368B2
公开(公告)日：2013-10-08
申请号：US12634219
申请日：2009-12-09
申请人： Peter P. Waskiewicz , Patrick Connor
发明人： Peter P. Waskiewicz , Patrick Connor
IPC分类号： H04L29/06
CPC分类号： H04L63/0263 , H04L63/0209
摘要： An embodiment may include network controller circuitry to be comprised in a host computer that includes a host processor to execute an operating system environment. The circuitry may be coupled to the processor, receive at least one packet via a network, store at least one firewall filter parameter set, and execute, based at least in part upon the parameter set and packet, at least one firewall filter action involving, at least in part, the packet. The action may implement, at least in part, at least one firewall rule supplied by a firewall application to an interface of a driver associated with the circuitry. The application may be executed, at least in part, in the environment. The circuitry may generate and store the parameter set based at least in part upon at least one command from the driver. The command may be based at least in part upon the rule.
摘要翻译：实施例可以包括要包括在主计算机中的网络控制器电路，其包括主机处理器以执行操作系统环境。电路可以耦合到处理器，经由网络接收至少一个分组，存储至少一个防火墙过滤器参数集，并且至少部分地基于参数集和分组来执行至少一个防火墙过滤器动作，至少部分是包。该动作可以至少部分地实现由防火墙应用提供给与该电路相关联的驱动器的接口的至少一个防火墙规则。该应用可以至少部分地在环境中执行。该电路可以至少部分地基于来自驾驶员的至少一个命令来生成和存储参数集。该命令至少可以部分地基于规则。

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