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    • 2. 发明授权
    • Differential impedance matching circuit and method with harmonic suppression
    • 差分阻抗匹配电路及谐波抑制方法
    • US07755448B2
    • 2010-07-13
    • US11970237
    • 2008-01-07
    • Attila ZolomyPeter OnodyTibor Toro
    • Attila ZolomyPeter OnodyTibor Toro
    • H03H7/38
    • H03H7/38
    • Matching network circuits and a method are shown for suppressing a harmonic frequency in a matching network. The circuits and method involve impedance matching first and second differential input nodes to a single ended output node using a first reactive impedance selected to pass a resonant frequency. They also involve suppressing a harmonic frequency of a common mode signal presented at the first and second differential input nodes by providing a series resonance from the first and second differential input nodes to a radio frequency ground potential, where the series resonance is selected to pass the harmonic frequency to the radio frequency ground potential.
    • 示出了匹配的网络电路和一种用于抑制匹配网络中的谐波频率的方法。 电路和方法包括使用选择的第一无功阻抗来使第一和第二差分输入节点与单端输出节点匹配以使谐振频率通过。 它们还涉及通过提供从第一和第二差分输入节点到射频地电位的串联谐振来抑制呈现在第一和第二差分输入节点处的共模信号的谐波频率,其中选择串联谐振以通过 谐波频率到射频地电位。
    • 5. 发明申请
    • Method and circuit for determining a slow clock calibration factor
    • 用于确定慢时钟校准因子的方法和电路
    • US20050221870A1
    • 2005-10-06
    • US10819056
    • 2004-04-06
    • Janos ErdelyiPeter Onody
    • Janos ErdelyiPeter Onody
    • H03L1/00H04B1/16H03M1/38
    • H03L1/00
    • Shown is a method and circuit for determining a calibration factor between a fast, high accuracy clock signal and a slow, low accuracy clock signal, which can be realised with a minimum number of electronic units, and which obtains the calibration factor in a very short time, thus minimising power consumption of the circuit. The present invention operates by counting the number of cycles of a high accuracy clock signal during a single cycle of a low accuracy clock signal to obtain a first number representing the number of cycles counted and then successively summing the first number until a sum of the first numbers reaches a first predetermined value. The count of the number of summing operations required to reach the first predetermined value is then used to determine the calibration parameter, which is proportional to the number of summing operations.
    • 示出了用于确定快速,高精度时钟信号与慢速,低精度时钟信号之间的校准因子的方法和电路,其可以用最小数量的电子单元实现,并且在非常短的时间内获得校准因子 时间,从而最小化电路的功耗。 本发明通过在低精度时钟信号的单个周期期间对高精度时钟信号的周期数进行计数来获得表示所计数的周期数的第一数字,然后连续求和第一个数,直到第一个 数字达到第一预定值。 然后使用达到第一预定值所需的求和操作次数的计数来确定与求和操作次数成比例的校准参数。