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    • 3. 发明申请
    • Multi-Standard Transceiver, Device and Method
    • 多标准收发器,设备和方法
    • US20120264381A1
    • 2012-10-18
    • US13087928
    • 2011-04-15
    • Carsten EisenhutPeter LaaserJens Kissing
    • Carsten EisenhutPeter LaaserJens Kissing
    • H04W88/02
    • H04B1/525H04B1/406H04W52/281H04W52/367
    • A multi-standard transceiver includes a first subunit configured to perform signal processing according to a first communication standard and a second subunit configured to perform signal processing according to a second communication standard. Furthermore, the multi-standard transceiver includes an interference cancellation unit configured to drive an estimated interference signal from a first signal generated by the first subunit by performing the signal processing according to the first communication standard, and perform interference cancellation on a second signal generated by the second subunit by performing the signal processing according to the second communication standard based on the estimated interference signal.
    • 多标准收发器包括被配置为根据第一通信标准执行信号处理的第一子单元和被配置为根据第二通信标准执行信号处理的第二子单元。 此外,多标准收发器包括:干扰消除单元,被配置为通过执行根据第一通信标准的信号处理来驱动来自由第一子单元生成的第一信号的估计干扰信号,并且对由第一通信标准产生的第二信号执行干扰消除, 所述第二子单元通过基于所估计的干扰信号执行根据所述第二通信标准的信号处理。
    • 4. 发明授权
    • Line driver for transmitting data
    • 用于传输数据的线路驱动程序
    • US07212038B2
    • 2007-05-01
    • US10485336
    • 2002-07-25
    • Peter GregoriusArmin HannebergPeter Laaser
    • Peter GregoriusArmin HannebergPeter Laaser
    • H03K19/094
    • H04L25/028H04L25/0272H04L25/0292
    • A line driver (3) for transmitting data with high bit rates, in particular for wire-bound data transmission in the full-duplex process, comprises a differential pair with differential pair transistors (14, 15) for generating transmission impulses as a function of the data to be transmitted, whereby the transmission impulses are preferably output via cascode transistors (16, 17), each with the differential pair transistors (14, 15) forming a cascode circuit, onto the data transmission line (8, 9) connected to the line driver (3). For reproducing the behaviour of the differential pair a replica differential pair with replica differential pair transistors (18, 19) is provided, generating replica impulses corresponding to the transmission impulses, which replica impulses can be fed via replica cascode transistors (20, 21) to a hybrid integrated circuit (6) for effecting echo compensation in relation to impulses received via the data transmission line (8, 9)
    • 用于以高比特率发送数据的线路驱动器(3),特别是用于全双工过程中用于有线数据传输的线路驱动器(3)包括与差分对晶体管(14,15)的差分对,用于产生传输脉冲作为 要发送的数据,由此传输脉冲优选地通过共模共轭二极管(16,17)输出,每个都具有形成共源共栅电路的差分对晶体管(14,15)到与数据传输线(8,9)相连的数据传输线 线路驱动器(3)。 为了再现差分对的行为,提供了具有复制差分对晶体管(18,19)的复制差分对,产生对应于传输脉冲的复制脉冲,该复制脉冲可以经由复制共源共栅晶体管(20,21)馈送到 用于对通过数据传输线(8,9)接收的脉冲进行回波补偿的混合集成电路(6)
    • 6. 发明授权
    • Sigma-delta A/D converter
    • Sigma-ΔA / D转换器
    • US06498573B2
    • 2002-12-24
    • US10067099
    • 2002-02-04
    • Peter Laaser
    • Peter Laaser
    • H03M300
    • H03M3/32H03M3/496
    • Sigma-delta A/D converter having at least one analog signal input (1, 2) for applying an analog input signal, a subtraction element (3) having a plurality of capacitors (20) for sampling the input signal during a sampling phase, it being possible during an integration phase to switch the capacitors (20) to reference voltage sources (7, 8, 9) depending on control signals, an integrator (10) for integrating the output signal of the subtraction element (3) during the integration phase, a quantizer (13) for analog-to-digital conversion of the output signal of the integrator (10) for outputting a digitized output signal to a digital signal output (14), and having a control logic element (16) for generating the control signals in such a way that the current load of the reference voltage sources (7, 8, 9) is minimized during the integration phase.
    • 具有用于施加模拟输入信号的至少一个模拟信号输入(1,2)的Σ-ΔA/ D转换器,具有用于在采样阶段期间对输入信号进行采样的多个电容器(20)的减法元件(3) 在积分阶段可以根据控制信号将电容器(20)切换到参考电压源(7,8,9),用于在积分期间积分减法元件(3)的输出信号的积分器(10) 相位,用于对积分器(10)的输出信号进行模数转换的量化器(13),用于将数字化的输出信号输出到数字信号输出(14),并具有用于产生数字信号的控制逻辑元件(16) 控制信号使得在积分阶段期间参考电压源(7,8,9)的当前负载最小化。
    • 7. 发明授权
    • Amplifier output stage
    • 放大器输出级
    • US06411167B2
    • 2002-06-25
    • US09771911
    • 2001-01-29
    • Peter Laaser
    • Peter Laaser
    • H03F326
    • H03F3/3001H03F1/308
    • An amplifier output stage is described containing a preliminary stage, a final stage and a control device. The quiescent current that flows through transistors of the final stage is adjusted by the preliminary stage. For this, a current that is proportional to the quiescent current is generated in the control device from which control voltages are derived and controlled. The preliminary stage contains adjustable current sources for adjusting the quiescent current in a final step which are controlled by the control voltages.
    • 描述了放大器输出级,其包括初级,最后级和控制装置。 通过初级阶段调整流过最终级晶体管的静态电流。 为此,在控制装置中产生与静态电流成比例的电流,控制电压从该电流被导出和控制。 初级阶段包含可调节的电流源,用于调节由控制电压控制的最终步骤中的静态电流。
    • 8. 发明授权
    • Multi-standard transceiver, device and method
    • 多标准收发器,设备和方法
    • US08600435B2
    • 2013-12-03
    • US13087928
    • 2011-04-15
    • Carsten EisenhutPeter LaaserJens Kissing
    • Carsten EisenhutPeter LaaserJens Kissing
    • H04M1/00
    • H04B1/525H04B1/406H04W52/281H04W52/367
    • A multi-standard transceiver includes a first subunit configured to perform signal processing according to a first communication standard and a second subunit configured to perform signal processing according to a second communication standard. Furthermore, the multi-standard transceiver includes an interference cancellation unit configured to drive an estimated interference signal from a first signal generated by the first subunit by performing the signal processing according to the first communication standard, and perform interference cancellation on a second signal generated by the second subunit by performing the signal processing according to the second communication standard based on the estimated interference signal.
    • 多标准收发器包括被配置为根据第一通信标准执行信号处理的第一子单元和被配置为根据第二通信标准执行信号处理的第二子单元。 此外,多标准收发器包括:干扰消除单元,被配置为通过执行根据第一通信标准的信号处理来驱动来自由第一子单元生成的第一信号的估计干扰信号,并且对由第一通信标准产生的第二信号执行干扰消除, 所述第二子单元通过基于所估计的干扰信号执行根据所述第二通信标准的信号处理。