专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20140084381A1 PRECISION RESISTOR FOR NON-PLANAR SEMICONDUCTOR DEVICE ARCHITECTURE 有权
标题翻译：非平面半导体器件结构精密电阻器
公开(公告)号：US20140084381A1
公开(公告)日：2014-03-27
申请号：US13625698
申请日：2012-09-24
申请人： Jeng-Ya D. Yeh , Peter J. Vandervoorn , Walid M. Hafez , Chia-Hong Jan , Curtis Tsai , Joodong Park
发明人： Jeng-Ya D. Yeh , Peter J. Vandervoorn , Walid M. Hafez , Chia-Hong Jan , Curtis Tsai , Joodong Park
IPC分类号： H01L27/06 , H01L21/02
CPC分类号： H01L21/823431 , H01L27/0629 , H01L27/0886 , H01L28/20 , H01L29/66545 , H01L29/66795
摘要： Precision resistors for non-planar semiconductor device architectures are described. In a first example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. A resistor structure is disposed above the first semiconductor fin but not above the second semiconductor fin. A transistor structure is formed from the second semiconductor fin but not from the first semiconductor fin. In a second example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. An isolation region is disposed above the substrate, between the first and second semiconductor fins, and at a height less than the first and second semiconductor fins. A resistor structure is disposed above the isolation region but not above the first and second semiconductor fins. First and second transistor structures are formed from the first and second semiconductor fins, respectively.
摘要翻译：描述了用于非平面半导体器件结构的精密电阻器。在第一示例中，半导体结构包括设置在基板上方的第一和第二半导体翅片。电阻器结构设置在第一半导体鳍片上方，但不在第二半导体鳍片之上。晶体管结构由第二半导体鳍形成，但不由第一半导体鳍形成。在第二示例中，半导体结构包括设置在基板上方的第一和第二半导体翅片。隔离区设置在基板之上，位于第一和第二半导体鳍之间，并且在小于第一和第二半导体鳍片的高度处。电阻结构设置在隔离区域上方，但不在第一和第二半导体鳍片之上。第一和第二晶体管结构分别由第一和第二半导体鳍形成。

2. 发明授权

US08796772B2 Precision resistor for non-planar semiconductor device architecture 有权
公开(公告)号：US08796772B2
公开(公告)日：2014-08-05
申请号：US13625698
申请日：2012-09-24
申请人： Jeng-Ya D. Yeh , Peter J. Vandervoorn , Walid M. Hafez , Chia-Hong Jan , Curtis Tsai , Joodong Park
发明人： Jeng-Ya D. Yeh , Peter J. Vandervoorn , Walid M. Hafez , Chia-Hong Jan , Curtis Tsai , Joodong Park
IPC分类号： H01L21/70
CPC分类号： H01L21/823431 , H01L27/0629 , H01L27/0886 , H01L28/20 , H01L29/66545 , H01L29/66795
摘要： Precision resistors for non-planar semiconductor device architectures are described. In a first example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. A resistor structure is disposed above the first semiconductor fin but not above the second semiconductor fin. A transistor structure is formed from the second semiconductor fin but not from the first semiconductor fin. In a second example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. An isolation region is disposed above the substrate, between the first and second semiconductor fins, and at a height less than the first and second semiconductor fins. A resistor structure is disposed above the isolation region but not above the first and second semiconductor fins. First and second transistor structures are formed from the first and second semiconductor fins, respectively.

3. 发明授权

US08889508B2 Precision resistor for non-planar semiconductor device architecture 有权
标题翻译：用于非平面半导体器件结构的精密电阻器
公开(公告)号：US08889508B2
公开(公告)日：2014-11-18
申请号：US14313678
申请日：2014-06-24
申请人： Jeng-Ya D. Yeh , Peter J. Vandervoorn , Walid M. Hafez , Chia-Hong Jan , Curtis Tsai , Joodong Park
发明人： Jeng-Ya D. Yeh , Peter J. Vandervoorn , Walid M. Hafez , Chia-Hong Jan , Curtis Tsai , Joodong Park
IPC分类号： H01L21/8234 , H01L29/66 , H01L49/02
CPC分类号： H01L21/823431 , H01L27/0629 , H01L27/0886 , H01L28/20 , H01L29/66545 , H01L29/66795
摘要： Precision resistors for non-planar semiconductor device architectures are described. In a first example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. A resistor structure is disposed above the first semiconductor fin but not above the second semiconductor fin. A transistor structure is formed from the second semiconductor fin but not from the first semiconductor fin. In a second example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. An isolation region is disposed above the substrate, between the first and second semiconductor fins, and at a height less than the first and second semiconductor fins. A resistor structure is disposed above the isolation region but not above the first and second semiconductor fins. First and second transistor structures are formed from the first and second semiconductor fins, respectively.
摘要翻译：描述了用于非平面半导体器件结构的精密电阻器。在第一示例中，半导体结构包括设置在基板上方的第一和第二半导体翅片。电阻器结构设置在第一半导体鳍片上方，但不在第二半导体鳍片之上。晶体管结构由第二半导体鳍形成，但不由第一半导体鳍形成。在第二示例中，半导体结构包括设置在基板上方的第一和第二半导体翅片。隔离区设置在基板之上，位于第一和第二半导体鳍之间，并且在小于第一和第二半导体鳍片的高度处。电阻结构设置在隔离区域上方，但不在第一和第二半导体鳍片之上。第一和第二晶体管结构分别由第一和第二半导体鳍形成。

4. 发明申请

US20140308785A1 PRECISION RESISTOR FOR NON-PLANAR SEMICONDUCTOR DEVICE ARCHITECTURE 有权
公开(公告)号：US20140308785A1
公开(公告)日：2014-10-16
申请号：US14313678
申请日：2014-06-24
申请人： Jeng-Ya D. Yeh , Peter J. Vandervoorn , Walid M. Hafez , Chia-Hong Jan , Curtis Tsai , Joodong Park
发明人： Jeng-Ya D. Yeh , Peter J. Vandervoorn , Walid M. Hafez , Chia-Hong Jan , Curtis Tsai , Joodong Park
IPC分类号： H01L21/8234 , H01L29/66 , H01L49/02
CPC分类号： H01L21/823431 , H01L27/0629 , H01L27/0886 , H01L28/20 , H01L29/66545 , H01L29/66795
摘要： Precision resistors for non-planar semiconductor device architectures are described. In a first example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. A resistor structure is disposed above the first semiconductor fin but not above the second semiconductor fin. A transistor structure is formed from the second semiconductor fin but not from the first semiconductor fin. In a second example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. An isolation region is disposed above the substrate, between the first and second semiconductor fins, and at a height less than the first and second semiconductor fins. A resistor structure is disposed above the isolation region but not above the first and second semiconductor fins. First and second transistor structures are formed from the first and second semiconductor fins, respectively.

5. 发明申请

US20140291766A1 PLANAR DEVICE ON FIN-BASED TRANSISTOR ARCHITECTURE 有权
标题翻译：基于晶圆的晶体管架构的平面设备
公开(公告)号：US20140291766A1
公开(公告)日：2014-10-02
申请号：US13995755
申请日：2013-03-30
申请人： Walid M. Hafez , Peter J. Vandervoorn , Chia-Hong Jan
发明人： Walid M. Hafez , Peter J. Vandervoorn , Chia-Hong Jan
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L27/0886 , H01L21/823431 , H01L29/1608 , H01L29/161
摘要： Techniques are disclosed for forming a planar-like transistor device on a fin-based field-effect transistor (finFET) architecture during a finFET fabrication process flow. In some embodiments, the planar-like transistor can include, for example, a semiconductor layer which is grown to locally merge/bridge a plurality of adjacent fins of the finFET architecture and subsequently planarized to provide a high-quality planar surface on which the planar-like transistor can be formed. In some instances, the semiconductor merging layer can be a bridged-epi growth, for example, comprising epitaxial silicon. In some embodiments, such a planar-like device may assist, for example, with analog, high-voltage, wide-Z transistor fabrication. Also, provision of such a planar-like device during a finFET flow may allow for the formation of transistor devices, for example, exhibiting lower capacitance, wider Z, and/or fewer high electric field locations for improved high-voltage reliability, which may make such devices favorable for analog design, in some instances.
摘要翻译：公开了在finFET制造工艺流程期间在基于鳍片的场效应晶体管（finFET）架构上形成平面状晶体管器件的技术。在一些实施例中，平面状晶体管可以包括例如半导体层，该半导体层被生长以局部地合并/桥接finFET架构的多个相邻鳍片，并且随后被平坦化以提供高质量的平面表面，平面形晶体管。在一些情况下，半导体合并层可以是桥接外延生长，例如包括外延硅。在一些实施例中，这样的平面状器件可以辅助例如模拟，高电压，宽Z晶体管制造。此外，在finFET流动期间提供这样的平面状器件可以允许形成晶体管器件，例如，显示出更低的电容，更宽的Z和/或更少的高电场位置，以改善高电压可靠性，其可以在某些情况下，使这种设备有利于模拟设计。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式