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    • 1. 发明授权
    • Intelligent SCSI-2/DMA processor
    • 智能SCSI-2 / DMA处理器
    • US6018777A
    • 2000-01-25
    • US976683
    • 1997-11-24
    • Eugene L. ShrockPeter J. Bartlett
    • Eugene L. ShrockPeter J. Bartlett
    • G06F13/38G06F13/28
    • G06F13/387
    • A SCSI-2-and-DMA processor that has on a single integrated circuit a SCSI-2 interface for a SCSI-2 data bus that is at least two bytes wide and a DMA interface for a system data bus that is at least two bytes wide. This integrated circuit has an set of control registers and an on-chip processor such that the transfers involving SCSI-2 data transfers involving data words that have a width of at least two bytes can be processed and completed without burdening the remainder of the system. Substantially all that is needed of the system processor is to down load a very compact control program and then transfers between this integrated circuit and system RAM. The on-chip processor allows chaining of random length blocks of contiguous address data by using a chain mode of transfer which also pairs up any odd residue with a portion of the first word of the next block in the chain using on-chip processing.
    • SCSI-2和DMA处理器在单个集成电路上具有至少两个字节宽的SCSI-2数据总线的SCSI-2接口和至少两个字节的系统数据总线的DMA接口 宽。 该集成电路具有一组控制寄存器和片上处理器,使得涉及具有至少两个字节的宽度的数据字的SCSI-2数据传输的传输可以被处理和完成,而不会使系统的其余部分负担。 系统处理器所需的大部分内容是下载非常紧凑的控制程序,然后在该集成电路和系统RAM之间传输。 片上处理器允许通过使用链传输模式链接连续地址数据的随机长度块,其也使用片上处理将链中的任何奇数残余与链中的下一块的第一个字的一部分进行配对。