专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20120307545A1 Interleaved Bit Line Architecture for 2T2C Ferroelectric Memories 审中-公开
标题翻译： 2T2C铁电存储器的交错位线架构
公开(公告)号：US20120307545A1
公开(公告)日：2012-12-06
申请号：US13150885
申请日：2011-06-01
申请人： Hugh P. McAdams , Scott R. Summerfelt , Patrick M. Ndai
发明人： Hugh P. McAdams , Scott R. Summerfelt , Patrick M. Ndai
IPC分类号： G11C11/22
CPC分类号： G11C11/221
摘要： A ferroelectric memory with interleaved pairs of ferroelectric memory cells of the two-transistor, two-capacitor (2T2C) type. Each memory cell in a given pair is constructed as first and second portions, each portion including a transistor and a ferroelectric capacitor. Within each pair, a first portion of a second memory cell is physically located between the first and second portions of the first memory cell. As a result, complementary bit lines for adjacent columns are interleaved with one another. Each sense amplifier is associated with a multiplexer, so that the adjacent columns of the interleaved memory cells are supported by a single sense amplifier. Noise coupling among the bit lines is reduced, and the sense amplifiers can be placed along one side of the array, reducing the number of dummy cells required to eliminate edge cell effects.
摘要翻译：具有双晶体管，双电容器（2T2C）型的交错成对的铁电存储器单元的铁电存储器。给定对中的每个存储单元被构造为第一和第二部分，每个部分包括晶体管和铁电电容器。在每对内，第二存储单元的第一部分物理地位于第一存储单元的第一和第二部分之间。结果，用于相邻列的互补位线彼此交错。每个读出放大器与复用器相关联，使得交错存储器单元的相邻列由单个读出放大器支持。位线之间的噪声耦合减少，并且读出放大器可以沿着阵列的一侧放置，减少了消除边缘单元效应所需的虚拟单元的数量。

IPRDB

热门服务

关于我们

友情链接

联系方式