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1. 发明授权

US09459317B2 Mixed mode integrated circuit, method of providing a controllable test clock signal to a sub-circuitry of the mixed-mode integrated circuit and method of detecting current paths causing violations of electromagnetic compatibility standards in the mixed mode integrated circuit 有权
标题翻译：混合模式集成电路，向混合模式集成电路的子电路提供可控测试时钟信号的方法以及在混合模式集成电路中检测导致违反电磁兼容性标准的电流路径的方法
公开(公告)号：US09459317B2
公开(公告)日：2016-10-04
申请号：US14607798
申请日：2015-01-28
申请人： Pascal Kamel Abouda , Celine Hounaïda Abouda , Patrice Besse
发明人： Pascal Kamel Abouda , Celine Hounaïda Abouda , Patrice Besse
IPC分类号： H04L7/00 , G01R31/317 , G01R31/3167
CPC分类号： G01R31/31727 , G01R31/3167
摘要： A mixed mode integrated circuit, a method of providing a controllable test clock signal to a sub-circuitry of the mixed-mode integrated circuit and a method of detecting current paths causing violations of electromagnetic compatibility standards in the mixed mode integrated circuit are provided. The mixed mode integrated circuit 100 comprises in addition to a clock network 110 an integrated test clock signal generator 140 to generate test clock signals that are provided via controllable multiplexers 150, 160 to an analog and digital sub-circuitry, respectively, of the mixed-mode integrated circuit. The test clock signals are generated on basis of an input test clock signal having a controllable frequency. The clock network generates clock signals for the sub-circuitries that are used by the sub-circuitries under normal operational conditions. The controllable multiplexers provide either the test clock signal to a specific sub-circuitry or a clock signal received from the clock network.
摘要翻译：一种混合模式集成电路，一种向混合模式集成电路的子电路提供可控测试时钟信号的方法，以及一种检测混合模式集成电路中导致违反电磁兼容性标准的电流路径的方法。混合模式集成电路100除了时钟网络110之外还包括集成测试时钟信号发生器140，以产生经由可控多路复用器150,160分别提供给模拟和数字子电路的测试时钟信号，模式集成电路。基于具有可控频率的输入测试时钟信号产生测试时钟信号。时钟网络为在正常操作条件下的子电路使用的子电路产生时钟信号。可控多路复用器将测试时钟信号提供给从时钟网络接收的特定子电路或时钟信号。

2. 发明申请

US20150311193A1 A SEMICONDUCTOR DEVICE COMPRISING AN ESD PROTECTION DEVICE, AN ESD PROTECTION CIRCUITRY, AN INTEGRATED CIRCUIT AND A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE 有权
标题翻译：包含ESD保护装置的半导体器件，ESD保护电路，集成电路和制造半导体器件的方法
公开(公告)号：US20150311193A1
公开(公告)日：2015-10-29
申请号：US14419064
申请日：2012-08-22
申请人： Jean Philippe LAINE , Patrice BESSE
发明人： Jean Philippe LAINE , Patrice BESSE
IPC分类号： H01L27/02 , H01L29/10 , H01L29/06 , H01L27/06 , H01L21/8222
CPC分类号： H01L27/0259 , H01L21/8222 , H01L27/0255 , H01L27/0647 , H01L29/0649 , H01L29/1095
摘要： A semiconductor device is provided which comprises an ESD protection device. The ESD protection device is being formed by one or more pnp transistors which are present in the structure of the semiconductor device. The semiconductor device comprises two portions, of an isolated p-doped region which are separated by an N-doped region. Two p-doped regions are provided within the two portions. The p-dopant concentration of the two-doped region is higher than the p-dopant concentration of the isolated p-doped region. A first electrical contact is connected only via a highly doped p-contact region to the first p-doped region and a second electrical contact is connected only via another highly doped p-contact region to the second p-doped region.
摘要翻译：提供一种包括ESD保护装置的半导体器件。 ESD保护器件由存在于半导体器件的结构中的一个或多个pnp晶体管形成。半导体器件包括由N掺杂区域分离的隔离p掺杂区域的两个部分。在两个部分内设置两个p掺杂区域。双掺杂区域的p掺杂剂浓度高于分离的p掺杂区域的p掺杂剂浓度。第一电接触仅通过高度掺杂的p接触区域连接到第一p掺杂区域，并且第二电触点仅通过另一个高度掺杂的p接触区域连接到第二p掺杂区域。

3. 发明申请

US20150221633A1 SEMICONDUCTOR DEVICE COMPRISING AN ESD PROTECTION DEVICE, AN ESD PROTECTION CIRCUITRY, AN INTEGRATED CIRCUIT AND A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE 有权
标题翻译：包含ESD保护装置的半导体器件，ESD保护电路，集成电路和制造半导体器件的方法
公开(公告)号：US20150221633A1
公开(公告)日：2015-08-06
申请号：US14419029
申请日：2012-08-03
申请人： Jean Philippe Laine , Patrice Besse
发明人： Jean Philippe Laine , Patrice Besse
IPC分类号： H01L27/02 , H01L29/66
CPC分类号： H01L27/0259 , H01L27/0277 , H01L29/6625
摘要： A semiconductor device includes an ESD protection device. In a N-well, two P+ doped regions form a collector and emitter of a parasitic transistor of the ESD protection device. The N-well area between the P+ doped regions, forms a base of the parasitic transistor. At some distance away from the P+ doped regions an N+ doped region is provided. The N-well in between the N+ doped region and base of the transistor forms a parasitic resistor of the ESD protection device. The N+ doped region and the emitter of the transistor are coupled to each other via an electrical connection. The ESD protection device has a limited snapback behaviour and has a well-tunable trigger voltage.
摘要翻译：半导体器件包括ESD保护器件。在N阱中，两个P +掺杂区形成ESD保护器件的寄生晶体管的集电极和发射极。 P +掺杂区域之间的N阱区域形成寄生晶体管的基极。在距离P +掺杂区域一定距离处，提供了N +掺杂区域。 N +掺杂区域和晶体管的基极之间的N阱形成ESD保护器件的寄生电阻。晶体管的N +掺杂区域和发射极通过电连接彼此耦合。 ESD保护器件具有有限的快速恢复特性，并具有很好的触发电压。

4. 发明授权

US08456783B2 Integrated circuit, electronic device and ESD protection therefor 有权
标题翻译：集成电路，电子设备和ESD保护
公开(公告)号：US08456783B2
公开(公告)日：2013-06-04
申请号：US12597006
申请日：2007-04-27
申请人： Patrice Besse , Erwan Hemon , Philippe Lance
发明人： Patrice Besse , Erwan Hemon , Philippe Lance
IPC分类号： H02H9/00
CPC分类号： H01L27/0251
摘要： An integrated circuit comprises electro-static discharge (ESD) protection circuitry arranged to provide ESD protection to one or more external connector(s) of the integrated circuit. The ESD protection circuitry comprises at least one ESD protection component coupled to the one or more external connectors for providing ESD protection thereto. The ESD protection circuitry further comprises an ESD connector coupled to the one or more external connector(s), arranged to couple supplementary ESD protection to the one or more external connector(s).
摘要翻译：集成电路包括静电放电（ESD）保护电路，其布置成向集成电路的一个或多个外部连接器提供ESD保护。 ESD保护电路包括耦合到一个或多个外部连接器的至少一个ESD保护部件，用于向其提供ESD保护。 ESD保护电路还包括耦合到所述一个或多个外部连接器的ESD连接器，其布置成将辅助ESD保护耦合到所述一个或多个外部连接器。

5. 发明申请

US20090057833A1 SEMICONDUCTOR DEVICE STRUCTURE AND INTEGRATED CIRCUIT THEREFOR 有权
标题翻译：半导体器件结构及其集成电路
公开(公告)号：US20090057833A1
公开(公告)日：2009-03-05
申请号：US12282486
申请日：2006-03-13
申请人： Philippe Renaud , Patrice Besse , Amaury Gendron
发明人： Philippe Renaud , Patrice Besse , Amaury Gendron
IPC分类号： H01L27/06
CPC分类号： H01L27/0259 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device structure comprises a plurality of vertical layers and a plurality of conductive elements wherein the vertical layers and plurality of conductive elements co-operate to function as at least two active devices in parallel. The semiconductor device structure may also comprise a plurality of horizontal conductive elements wherein the structure is arranged to support at least two concurrent current flows, such that a first current flow is across the plurality of vertical conductive elements and a second current flow is across the plurality of horizontal conductive elements.
摘要翻译：半导体器件结构包括多个垂直层和多个导电元件，其中垂直层和多个导电元件协同工作以起到至少两个并联的有源器件的作用。半导体器件结构还可以包括多个水平导电元件，其中该结构被布置成支撑至少两个并流电流，使得第一电流流过多个垂直导电元件，并且第二电流跨越多个的水平导电元件。

6. 发明申请

US20080246345A1 Semiconductor Switch Arrangement and an Electronic Device 有权
标题翻译：半导体开关装置和电子装置
公开(公告)号：US20080246345A1
公开(公告)日：2008-10-09
申请号：US11573078
申请日：2005-08-03
申请人： Michel Zecri , Luca Bertolini , Patrice Besse , Maryse Bafleur , Nicolas Nolhier
发明人： Michel Zecri , Luca Bertolini , Patrice Besse , Maryse Bafleur , Nicolas Nolhier
IPC分类号： H03K17/082
CPC分类号： H03K17/0822
摘要： A semiconductor switch arrangement (300) comprises a bipolar transistor (302) and a semiconductor power switch (301) having an input node (306), an output node (304) and a control node (305) for allowing a current path to be formed between the input node (306) and the output node (307). The bipolar transistor (302) is coupled between the input node (306) and the control node (305) such that upon receiving an electro-static discharge pulse the bipolar transistor (302) allows a current to flow from the input node (306) to the control node (305) upon a pre-determined voltage being exceeded at the input node (306) to allow the control node (305) to cause a current to flow from the input node (306) to the output node (307). Thus, the bipolar transistor device protects the semiconductor switch device, such as an LDMOS device, against ESD, namely protection against power surges of, say, several amperes in less than 1 usec.
摘要翻译：半导体开关装置（300）包括双极晶体管（302）和具有输入节点（306）的半导体功率开关（301），输出节点（304）和控制节点（305），用于允许电流路径为形成在输入节点（306）和输出节点（307）之间。双极晶体管（302）耦合在输入节点（306）和控制节点（305）之间，使得当接收到静电放电脉冲时，双极晶体管（302）允许电流从输入节点（306）流出，在所述输入节点（306）超过预定电压以允许所述控制节点（305）使电流从所述输入节点（306）流向所述输出节点（307）的情况下，发送到所述控制节点（305）。因此，双极晶体管器件保护诸如LDMOS器件的半导体开关器件免受ESD，即在小于1 usec内防止诸如几安培的功率浪涌。

7. 发明授权

US10014289B2 Electrostatic discharge protection circuits and structures and methods of manufacture 有权
公开(公告)号：US10014289B2
公开(公告)日：2018-07-03
申请号：US15037714
申请日：2013-11-22
申请人： Patrice Besse , Jean-Philippe Laine , Eric Pierre Rolland
发明人： Patrice Besse , Jean-Philippe Laine , Eric Pierre Rolland
IPC分类号： H01L27/02 , H01L29/87 , H01L21/761 , H01L21/762 , H01L29/45 , H01L29/06
CPC分类号： H01L27/0262 , H01L21/761 , H01L21/76264 , H01L27/0259 , H01L27/0292 , H01L29/0649 , H01L29/45 , H01L29/87
摘要： An ESD protection circuit and device structure comprises five transistors, two PNP and three NPN. The five transistors are coupled together so that a first NPN and PNP pair constitute a first silicon controlled rectifier, SCR. The NPN transistor 102 of the first SCR and a third transistor of NPN type are coupled so that they constitute a Darlington pair. A further NPN and PNP pair are coupled together to form a second SCR with the collector of the PNP transistor of the first SCR being coupled with the emitter of the PNP transistor of the second SCR. The circuit is particularly suitable for high voltage triggering applications and two or more devices may be cascaded in series in order to further increase the triggering voltage.

8. 发明授权

US09620495B2 Semiconductor device and an integrated circuit comprising an ESD protection device, ESD protection devices and a method of manufacturing the semiconductor device 有权
公开(公告)号：US09620495B2
公开(公告)日：2017-04-11
申请号：US14427024
申请日：2012-09-12
申请人： Patrice Besse , Alexis Huot-Marchand , Jean-Philippe Laine , Alain Salles
发明人： Patrice Besse , Alexis Huot-Marchand , Jean-Philippe Laine , Alain Salles
IPC分类号： H01L27/02 , H01L29/74 , H01L21/8234 , H01L27/06
CPC分类号： H01L27/0262 , H01L21/8222 , H01L21/823418 , H01L21/823475 , H01L21/823481 , H01L27/0248 , H01L27/0623 , H01L29/7436
摘要： A semiconductor device is provided which comprises an ESD protection device. The structure of the semiconductor device comprises a p-doped isolated region in which a structure is manufactured which operates as a Silicon Controlled Rectifier which is coupled between an I/O pad and a reference voltage or ground voltage. The semiconductor device also comprises a pnp transistor which is coupled parallel to the Silicon Controlled Rectifier. The base of the transistor is coupled to the gate of the Silicon Controlled Rectifier. In an optional embodiment, the base and gate are also coupled to the I/O pad.

9. 发明申请

US20160156180A1 ELECTROSTATIC DISCHARGE PROTECTION 有权
标题翻译：静电放电保护
公开(公告)号：US20160156180A1
公开(公告)日：2016-06-02
申请号：US14702804
申请日：2015-05-04
申请人： PATRICE BESSE , PHILIPPE GIVELIN , JEAN PHILIPPE LAINE
发明人： PATRICE BESSE , PHILIPPE GIVELIN , JEAN PHILIPPE LAINE
IPC分类号： H02H9/04
CPC分类号： H02H9/046 , H01L27/0248
摘要： An electrostatic discharge protection circuit comprises at least two electrostatic discharge protection units connected in series between respective pairs of at least three input terminals, one of the input terminals being a reference input terminal. Each of the units comprises a silicon controlled rectifier and a current mirror. The output of the silicon controlled rectifier constitutes a first output of the respective unit and is connected to an input terminal of the circuit. The output of the current mirror constitutes a second output of the respective unit and is connected with the reference input terminal of the circuit. Thus the units are connected in series but the output terminals of the current mirrors are all connected with the reference input terminal, which may be a ground terminal, so as to minimise the breakdown resistance of the circuit.
摘要翻译：静电放电保护电路包括至少两个静电放电保护单元，其串联连接在各对至少三个输入端子之间，其中一个输入端子是参考输入端子。每个单元包括可控硅整流器和电流镜。可控硅整流器的输出构成相应单元的第一输出，并连接到电路的输入端。电流镜的输出构成各单元的第二输出，并与电路的基准输入端相连。因此，这些单元串联连接，而电流镜的输出端全部与可能是接地端子的参考输入端子相连，以便使电路的耐击穿电阻最小化。

10. 发明申请

US20150098160A1 PROTECTION CIRCUIT AND A GATE DRIVING CIRCUITRY 有权
标题翻译：保护电路和门驱动电路
公开(公告)号：US20150098160A1
公开(公告)日：2015-04-09
申请号：US14394675
申请日：2012-04-19
申请人： Yuan Gao , Patrice Besse , Thierry Laplagne
发明人： Yuan Gao , Patrice Besse , Thierry Laplagne
IPC分类号： H02H3/28
CPC分类号： H02H3/28 , H03K17/0822 , H03K17/102
摘要： A protection circuit and a gate driving circuitry. The protection circuit is for protecting a p-type back-to-back MOS switch. The circuit receives an input driving signal and provides a driving output signal to common gates of the p-type back-to-back MOS switch. The circuit comprises a driving signal insulation switch for disconnecting the common gate of the p-type back-to-back MOS switch from the received input driving signal when the voltage of the common gates is larger than the supply voltage of the circuit. The circuit further comprises a gate source coupling switch for coupling a voltage received at the common source of the p-type back-to-back MOS switch to the common gate if a received voltage at the common sources is larger than a reference voltage Vref.
摘要翻译：保护电路和栅极驱动电路。保护电路用于保护p型背对背MOS开关。电路接收输入驱动信号，并向p型背对背MOS开关的公共栅极提供驱动输出信号。该电路包括驱动信号绝缘开关，用于当公共栅极的电压大于电路的电源电压时，从所接收的输入驱动信号中断开p型背对背MOS开关的公共栅极。该电路还包括一个栅极耦合开关，用于在公共源的接收电压大于参考电压Vref时，将在p型背靠背MOS开关的公共源接收的电压耦合到公共栅极。

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