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1. 发明授权

US08246284B2 Stacked load-lock apparatus and method for high throughput solar cell manufacturing 失效
标题翻译：用于高产量太阳能电池制造的堆叠式加载锁定装置和方法
公开(公告)号：US08246284B2
公开(公告)日：2012-08-21
申请号：US12398769
申请日：2009-03-05
申请人： Peter G. Borden
发明人： Peter G. Borden
IPC分类号： H01L21/677
CPC分类号： H01L21/67201 , C23C14/566 , C23C16/4401 , C23C16/54
摘要： An apparatus with a plurality of load-lock chambers stacked having independently controlled pressures within their interior regions is provided. According to one or more embodiments, each load-lock chamber includes a pump valve connected to a pump line and a vent valve connected to a vent line to independently control the changes of pressure within the interior regions of the chambers. Methods for conveying substrates held within these chambers from the apparatus to one or more processing chambers, which may be in-line, are also provided.
摘要翻译：提供了具有多个在其内部区域内具有独立控制压力的负载锁定室的装置。根据一个或多个实施例，每个加载锁定室包括连接到泵管线的泵阀和连接到排气管线的排放阀，以独立地控制室内部区域内的压力变化。还提供了将保持在这些室内的基板从设备输送到可以是在线的一个或多个处理室的方法。

2. 发明申请

US20100132774A1 Thin Film Silicon Solar Cell Device With Amorphous Window Layer 审中-公开
标题翻译：具有非晶窗口层的薄膜硅太阳能电池器件
公开(公告)号：US20100132774A1
公开(公告)日：2010-06-03
申请号：US12332608
申请日：2008-12-11
申请人： Peter G. Borden
发明人： Peter G. Borden
IPC分类号： H01L31/00 , H01L31/0232
CPC分类号： H01L31/075 , H01L31/03685 , Y02E10/545 , Y02E10/548
摘要： Photovoltaic devices and methods of manufacture are provided. In an embodiment, the devices comprise a micro-crystal silicon cell having an amorphous silicon layer formed on the micro-crystal cell.
摘要翻译：提供了光伏器件和制造方法。在一个实施例中，器件包括具有形成在微晶体单元上的非晶硅层的微晶硅单元。

3. 发明授权

US07379185B2 Evaluation of openings in a dielectric layer 失效
标题翻译：评估电介质层中的开口
公开(公告)号：US07379185B2
公开(公告)日：2008-05-27
申请号：US10979397
申请日：2004-11-01
申请人： Peter G. Borden , Jiping Li , Edgar Genio
发明人： Peter G. Borden , Jiping Li , Edgar Genio
IPC分类号： G01N21/55
CPC分类号： G01N21/171 , G01N21/95684 , G01N21/95692 , H01L22/20
摘要： A patterned dielectric layer is evaluated by measuring reflectance of a region which has openings. A heating beam may be chosen for having reflectance from an underlying conductive layer that is several times greater than absorptance, to provide a heightened sensitivity to presence of residue and/or changes in dimension of the openings. Reflectance may be measured by illuminating the region with a heating beam modulated at a preset frequency, and measuring power of a probe beam that reflects from the region at the preset frequency. Openings of many embodiments have sub-wavelength dimensions (i.e. smaller than the wavelength of the heating beam). The underlying conductive layer may be patterned into links of length smaller than the diameter of heating beam, so that the links float to a temperature higher than a corresponding temperature attained by a continuous trace that transfers heat away from the illuminated region by conduction.
摘要翻译：通过测量具有开口的区域的反射率来评估图案化的介电层。加热束可以被选择为具有比吸收率大几倍的下层导电层的反射率，以提供对残留物的存在和/或开口尺寸变化的更高的灵敏度。反射率可以通过以预设频率调制的加热光束照射该区域并测量从预设频率的区域反射的探测光束的功率来测量。许多实施例的开口具有亚波长尺寸（即小于加热束的波长）。底层导电层可以被图案化成长度小于加热束直径的链节，使得链节浮动到高于通过传导将热量从照射区域传递的连续迹线获得的相应温度的温度。

4. 发明申请

US20080023065A1 Thin film photovoltaic module wiring for improved efficiency 审中-公开
标题翻译：薄膜光伏模块布线提高效率
公开(公告)号：US20080023065A1
公开(公告)日：2008-01-31
申请号：US11492277
申请日：2006-07-25
申请人： Peter G. Borden , David J. Eaglesham
发明人： Peter G. Borden , David J. Eaglesham
IPC分类号： H01L31/00
CPC分类号： H01L31/0465 , Y02E10/50
摘要： The present invention relates to configuring and wiring together cells in TF PV modules. According to one aspect, cells are fabricated on one plane on a top surface of a substrate, with wiring patterned on a parallel plane, and vias formed to provide connections between the cell plane and wiring plane. In one embodiment, the wiring plane is on the back surface of the substrate and vias are formed through the substrate. In another embodiment, the wiring plane is on the top surface of the substrate underneath the cell plane and an insulating layer, with the vias formed through the insulating layer. In another embodiment, the cell plane formed on the top surface includes superstrate cells that are illuminated through a transparent substrate, with an insulator between the cell plane and an upper wiring plane. According to another aspect, the heavy bus bar connections in the wiring plane can carry large currents and do not block light impinging on the cells. According to further aspects, the wiring plane enables use of parallel cell connections that provide immunity to shading, as described above. Moreover, these connections can be wired in a variety of methods, allowing use of series-parallel arrangements so that, for example, local regions could be parallel connected while larger regions series connected.
摘要翻译：本发明涉及将光伏组件中的电池配置和接线在一起。根据一个方面，在衬底的顶表面上的一个平面上制造电池，其中布线在平行平面上图案化，并且形成通孔以提供电池平面和布线平面之间的连接。在一个实施例中，布线平面位于基板的背面，并且穿过基板形成通孔。在另一个实施例中，布线平面位于单元平面下方的基板的顶表面和绝缘层，通孔通过绝缘层形成。在另一个实施例中，形成在顶表面上的单元平面包括通过透明基板照射的透明单元，在单元平面和上布线平面之间具有绝缘体。根据另一方面，布线平面中的重型母线连接可以承载大电流并且不阻挡撞击电池的光。根据另外的方面，如上所述，布线平面能够使用提供对阴影的免疫力的并行单元连接。此外，这些连接可以以各种方式布线，允许使用串并联装置，使得例如局部区域可以并联连接，而较大区域串联连接。

5. 发明授权

US07301619B2 Evaluating a multi-layered structure for voids 有权
标题翻译：评估空洞的多层结构
公开(公告)号：US07301619B2
公开(公告)日：2007-11-27
申请号：US11454332
申请日：2006-06-16
申请人： Peter G. Borden , Ji-Ping Li
发明人： Peter G. Borden , Ji-Ping Li
IPC分类号： G01N21/88
CPC分类号： G01N21/1717 , G01N21/171 , G01N21/21 , G01N21/211 , G01N21/8422 , G01N21/9501 , G01N21/9505 , G01N21/95607 , G01N21/95692 , G01N2021/1748 , G01N2021/216 , G01R31/2648 , G01R31/2656 , H01L22/12
摘要： A method and apparatus measure properties of two layers of a damascene structure (e.g. a silicon wafer during fabrication), and use the two measurements to identify a location as having voids. The two measurements may be used in any manner, e.g. compared to one another, and voids are deemed to be present when the two measurements diverge from each other. In response to the detection of voids, a process parameter used in fabrication of the damascene structure may be changed, to reduce or eliminate voids in to-be-formed structures.
摘要翻译：一种方法和装置测量两层镶嵌结构（例如在制造期间的硅晶片）的性质，并且使用两个测量来将位置识别为具有空隙。这两个测量可以以任何方式使用，例如，相比之下，当两个测量彼此偏离时，视为存在空白。响应于空隙的检测，可以改变在镶嵌结构的制造中使用的工艺参数，以减少或消除要形成的结构中的空隙。

6. 发明授权

US07064822B2 Evaluating a multi-layered structure for voids 失效
标题翻译：评估空洞的多层结构
公开(公告)号：US07064822B2
公开(公告)日：2006-06-20
申请号：US11114300
申请日：2005-04-25
申请人： Peter G. Borden , Ji-Ping Li
发明人： Peter G. Borden , Ji-Ping Li
IPC分类号： G01N21/88
CPC分类号： G01N21/1717 , G01N21/171 , G01N21/21 , G01N21/211 , G01N21/8422 , G01N21/9501 , G01N21/9505 , G01N21/95607 , G01N21/95692 , G01N2021/1748 , G01N2021/216 , G01R31/2648 , G01R31/2656 , H01L22/12
摘要： A method and apparatus measure properties of two layers of a damascene structure (e.g. a silicon wafer during fabrication), and use the two measurements to identify a location as having voids. One of the two measurements is of resistance per unit length. The two measurements may be used in any manner, e.g. compared to one another, and voids are deemed to be present when the two measurements diverge from each other. In response to the detection of voids, a process parameter used in fabrication of the damascene structure may be changed, to reduce or eliminate voids in to-be-formed structures.
摘要翻译：一种方法和装置测量两层镶嵌结构（例如在制造期间的硅晶片）的性质，并且使用两个测量来将位置识别为具有空隙。两个测量中的一个是每单位长度的电阻。这两个测量可以以任何方式使用，例如，相比之下，当两个测量彼此偏离时，视为存在空白。响应于空隙的检测，可以改变在镶嵌结构的制造中使用的工艺参数，以减少或消除要形成的结构中的空隙。

7. 发明授权

US06971791B2 Identifying defects in a conductive structure of a wafer, based on heat transfer therethrough 有权
标题翻译：基于通过其中的热传递识别晶片的导电结构中的缺陷
公开(公告)号：US06971791B2
公开(公告)日：2005-12-06
申请号：US10090287
申请日：2002-03-01
申请人： Peter G. Borden , Ji-Ping Li
发明人： Peter G. Borden , Ji-Ping Li
IPC分类号： G01N25/72 , H01L23/544 , G01R31/26 , G01N21/00
CPC分类号： H01L22/34 , G01N25/72 , H01L2924/3011
摘要： Heat is applied to a conductive structure that includes one or more vias, and the temperature at or near the point of heat application is measured. The measured temperature indicates the integrity or the defectiveness of various features (e.g. vias and/or traces) in the conductive structure, near the point of heat application. Specifically, a higher temperature measurement (as compared to a measurement in a reference structure) indicates a reduced heat transfer from the point of heat application, and therefore indicates a defect. The reference structure can be in the same die as the conductive structure (e.g. to provide a baseline) or outside the die but in the same wafer (e.g. in a test structure) or outside the wafer (e.g. in a reference wafer), depending on the embodiment.
摘要翻译：将热施加到包括一个或多个通孔的导电结构，并且测量在加热点处或附近的温度。测量的温度表示导热结构中靠近加热点的各种特征（例如通路和/或迹线）的完整性或缺陷。具体而言，较高的温度测量（与参考结构中的测量相比）表示从加热点减少的热传递，因此表示缺陷。参考结构可以与导电结构（例如，提供基线）或模具外部在相同的晶片（例如，在测试结构中）或晶片外部（例如，在参考晶片中）处于相同的裸片中，这取决于该实施例。

8. 发明授权

US06940592B2 Calibration as well as measurement on the same workpiece during fabrication 有权
标题翻译：在制造过程中对同一工件进行校准和测量
公开(公告)号：US06940592B2
公开(公告)日：2005-09-06
申请号：US09974571
申请日：2001-10-09
申请人： Peter G. Borden , Jiping Li , Jon Madsen
发明人： Peter G. Borden , Jiping Li , Jon Madsen
IPC分类号： G01N21/27 , G01N21/55 , G01N21/95 , G01J3/28 , G01B11/28 , G01N21/00 , G01N21/86
CPC分类号： G01N21/9501 , G01N21/274 , G01N21/55 , G01N21/95607
摘要： Two more measurements are made on the same workpiece, during fabrication. Each measurement may be made employing a different process. The measurements are used together to determine a property of the workpiece. For example, multiple measurements from a first process are used with a predetermined value of the property of interest in a simulator to generate a simulated value of a signal to be measured in a second process. One or more such simulated values and a measured value are used to identify a value of the property of interest. When the workpiece's property is found to not match the specification, a process control parameter used in the workpiece's fabrication is adjusted, thereby to implement process control.
摘要翻译：在制造过程中，在同一工件上进行两次测量。可以使用不同的处理来进行每个测量。这些测量结果一起用于确定工件的特性。例如，来自第一处理的多个测量与模拟器中感兴趣的属性的预定值一起使用，以在第二过程中产生要测量的信号的模拟值。使用一个或多个这样的模拟值和测量值来识别感兴趣的属性的值。当发现工件的特性不符合规范时，调整工件制造中使用的过程控制参数，从而实现过程控制。

9. 发明授权

US06878559B2 Measurement of lateral diffusion of diffused layers 有权
公开(公告)号：US06878559B2
公开(公告)日：2005-04-12
申请号：US10253121
申请日：2002-09-23
申请人： Peter G. Borden , G. Jonathan Kluth , Eric Paton
发明人： Peter G. Borden , G. Jonathan Kluth , Eric Paton
IPC分类号： G01N21/21 , G01N21/84 , G01N21/95 , G01N21/956 , G01R31/311 , H01L23/544 , H01L21/66
CPC分类号： H01L22/34 , G01N21/21 , G01N21/9501 , G01N21/95607 , G01N2021/8416 , G01N2201/0691 , G01R31/311 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Any semiconductor wafer fabrication process may be changed to monitor lateral abruptness of doped layers as an additional step in the wafer fabrication process. In one embodiment, a test structure including one or more doped regions is formed in a production wafer (e.g. simultaneously with one or more transistors) and one or more dimension(s) of the test structure are measured, and used as an estimate of lateral abruptness in other doped regions in the wafer, e.g. in the simultaneously formed transistors. Doped regions in test structures can be located at regularly spaced intervals relative to one another, or alternatively may be located with varying spacings between adjacent doped regions. Alternatively or in addition, multiple test structures may be formed in a single wafer, with doped regions at regular spatial intervals in each test structure, while different test structures have different spatial intervals.

10. 发明授权

US06489801B1 Apparatus and method for evaluating a semiconductor wafer 有权
标题翻译：用于评估半导体晶片的装置和方法
公开(公告)号：US06489801B1
公开(公告)日：2002-12-03
申请号：US09544280
申请日：2000-04-06
申请人： Peter G. Borden , Regina G. Nijmeijer , Jiping Li
发明人： Peter G. Borden , Regina G. Nijmeijer , Jiping Li
IPC分类号： G01R3126
CPC分类号： G01N21/1717 , G01R31/2648 , G01R31/2656 , G01R31/311 , H01L22/12
摘要： An apparatus and method uses diffusive modulation (without generating a wave of carriers) for measuring a material property (such as any one or more of: mobility, doping, and lifetime) that is used in evaluating a semiconductor wafer. The measurements are carried out in a small area, for use on wafers having patterns for integrated circuit dice. The measurements are based on measurement of reflectance, for example as a function of carrier concentration. In one implementation, the semiconductor wafer is illuminated with two beams, one with photon energy above the bandgap energy of the semiconductor, and another with photon energy near or below the bandgap. The diameters of the two beams relative to one another are varied to extract additional information about the semiconductor material, for use in measuring, e.g. lifetime.
摘要翻译：一种装置和方法使用扩散调制（不产生载波）来测量用于评估半导体晶片的材料性质（例如，迁移率，掺杂和寿命中的任何一个或多个）。测量在小面积上进行，用于具有用于集成电路芯片的图案的晶片。测量是基于反射率的测量，例如作为载流子浓度的函数。在一个实施方案中，用两个光束照射半导体晶片，一个光子能量高于半导体的带隙能量，另一个具有接近或低于带隙的光子能量。改变两个光束相对于彼此的直径以提取关于半导体材料的附加信息，以用于测量例如半导体材料。一生。

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