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1. 发明授权

US09054215B2 Patterning of vertical nanowire transistor channel and gate with directed self assembly 有权
标题翻译：垂直纳米线晶体管沟道和栅极的定向自组装图案化
公开(公告)号：US09054215B2
公开(公告)日：2015-06-09
申请号：US13719113
申请日：2012-12-18
申请人： Paul A. Nyhus , Swaminathan Sivakumar
发明人： Paul A. Nyhus , Swaminathan Sivakumar
IPC分类号： H01L21/8234 , H01L29/78 , H01L29/775 , H01L29/66 , B82Y10/00 , B82Y40/00 , H01L29/423 , H01L29/06 , H01L29/16
CPC分类号： H01L21/823487 , B82Y10/00 , B82Y40/00 , H01L21/02532 , H01L21/02603 , H01L21/02642 , H01L21/28123 , H01L21/30625 , H01L21/823412 , H01L21/823418 , H01L21/823437 , H01L27/088 , H01L29/0676 , H01L29/16 , H01L29/42376 , H01L29/42392 , H01L29/517 , H01L29/66666 , H01L29/66742 , H01L29/775 , H01L29/7827 , H01L29/78618 , H01L29/78642 , H01L29/78651 , H01L29/78684 , H01L29/78696
摘要： Directed self-assembly (DSA) material, or di-block co-polymer, to pattern features that ultimately define a channel region a gate electrode of a vertical nanowire transistor, potentially based on one lithographic operation. In embodiments, DSA material is confined within a guide opening patterned using convention lithography. In embodiments, channel regions and gate electrode materials are aligned to edges of segregated regions within the DSA material.
摘要翻译：定向自组装（DSA）材料或二嵌段共聚物可能基于一个光刻操作来最终限定垂直纳米线晶体管的栅电极的通道区域的特征。在实施例中，DSA材料被限制在使用常规光刻图案化的引导开口内。在实施例中，沟道区域和栅电极材料与DSA材料内的分离区域的边缘对准。

2. 发明授权

US07632610B2 Sub-resolution assist features 有权
标题翻译：子分辨率辅助功能
公开(公告)号：US07632610B2
公开(公告)日：2009-12-15
申请号：US10933625
申请日：2004-09-02
申请人： Charles H. Wallace , Paul A. Nyhus , Swaminathan (Sam) Sivakumar
发明人： Charles H. Wallace , Paul A. Nyhus , Swaminathan (Sam) Sivakumar
IPC分类号： G03F1/00
CPC分类号： G03F1/36
摘要： Systems and techniques relating to the layout and use of sub-resolution assist features. In one implementation, a mask includes a first feature and a second feature separated from each other by a gap and a sub-resolution assist feature bridging the gap between the first feature and the second feature.
摘要翻译：与分辨率辅助功能的布局和使用相关的系统和技术。在一个实现中，掩模包括通过间隙彼此分离的第一特征和第二特征，以及桥接第一特征和第二特征之间的间隙的子分辨率辅助特征。

3. 发明授权

US09153477B2 Directed self assembly of block copolymers to form vias aligned with interconnects 有权
标题翻译：嵌段共聚物的定向自组装形成与互连对准的通孔
公开(公告)号：US09153477B2
公开(公告)日：2015-10-06
申请号：US13631197
申请日：2012-09-28
申请人： Paul A. Nyhus , Swaninathan Sivakumar , Robert Bristol
发明人： Paul A. Nyhus , Swaninathan Sivakumar , Robert Bristol
IPC分类号： H01L21/768 , H01L21/033 , H01L21/311 , H01L23/522
CPC分类号： H01L21/76877 , H01L21/0337 , H01L21/31144 , H01L21/76811 , H01L21/76816 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A method of an aspect includes forming an interconnect line etch opening in a hardmask layer. The hardmask layer is over a dielectric layer that has an interconnect line disposed therein. The interconnect line etch opening is formed aligned over the interconnect line. A block copolymer is introduced into the interconnect line etch opening. The block copolymer is assembled to form a plurality of assembled structures that are spaced along a length of the interconnect line etch opening. An assembled structure is directly aligned over the interconnect line that is disposed within the dielectric layer.
摘要翻译：一方面的方法包括在硬掩模层中形成互连线蚀刻开口。硬掩模层位于其中布置有互连线的电介质层上。互连线蚀刻开口在互连线上形成对准。将嵌段共聚物引入到互连线蚀刻开口中。嵌段共聚物被组装以形成沿着互连线蚀刻开口的长度间隔开的多个组装结构。组装的结构在设置在电介质层内的互连线上直接对准。

4. 发明申请

US20150093702A1 EXPOSURE ACTIVATED CHEMICALLY AMPLIFIED DIRECTED SELF-ASSEMBLY (DSA) FOR BACK END OF LINE (BEOL) PATTERN CUTTING AND PLUGGING 有权
标题翻译：用于线后退（BEOL）图案切割和插入的接触激活化学引导的自组装（DSA）
公开(公告)号：US20150093702A1
公开(公告)日：2015-04-02
申请号：US14039140
申请日：2013-09-27
申请人： Paul A. Nyhus , Eungnak Han , Swaminathan Sivakumar , Ernisse S. Putna
发明人： Paul A. Nyhus , Eungnak Han , Swaminathan Sivakumar , Ernisse S. Putna
IPC分类号： H01L21/768 , G03F7/039 , H01L21/027
CPC分类号： G03F7/0392 , B81C1/00428 , B81C2201/0149 , G03F7/0002 , G03F7/0045 , G03F7/038 , G03F7/039 , G03F7/11 , G03F7/16 , G03F7/2004 , G03F7/2037 , G03F7/26 , H01L21/0337 , H01L21/31058 , H01L21/32 , H01L21/3205 , H01L21/32139 , H01L21/76816
摘要： Self-aligned via and plug patterning for back end of line (BEOL) interconnects are described. In an example, a structure for directed self-assembly includes a substrate and a block co-polymer structure disposed above the substrate. The block co-polymer structure has a polystyrene (PS) component and a polymethyl methacrylate (PMMA) component. One of the PS component or the PMMA component is photosensitive.
摘要翻译：描述了用于后端（BEOL）互连的自对准通孔和插头图案。在一个示例中，用于定向自组装的结构包括设置在衬底上方的衬底和嵌段共聚物结构。嵌段共聚物结构具有聚苯乙烯（PS）组分和聚甲基丙烯酸甲酯（PMMA）组分。 PS组件或PMMA组件之一是光敏的。

5. 发明授权

US09530688B2 Directed self assembly of block copolymers to form vias aligned with interconnects 有权
公开(公告)号：US09530688B2
公开(公告)日：2016-12-27
申请号：US14822865
申请日：2015-08-10
申请人： Paul A. Nyhus , Swaminathan Sivakumar , Robert Bristol
发明人： Paul A. Nyhus , Swaminathan Sivakumar , Robert Bristol
IPC分类号： H01L21/4763 , H01L21/768 , H01L23/522 , H01L21/033 , H01L21/311
CPC分类号： H01L21/76877 , H01L21/0337 , H01L21/31144 , H01L21/76811 , H01L21/76816 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A method of an aspect includes forming an interconnect line etch opening in a hardmask layer. The hardmask layer is over a dielectric layer that has an interconnect line disposed therein. The interconnect line etch opening is formed aligned over the interconnect line. A block copolymer is introduced into the interconnect line etch opening. The block copolymer is assembled to form a plurality of assembled structures that are spaced along a length of the interconnect line etch opening. An assembled structure is directly aligned over the interconnect line that is disposed within the dielectric layer.

6. 发明申请

US20140053117A1 TECHNIQUES FOR PHASE TUNING FOR PROCESS OPTIMIZATION 有权
标题翻译：用于过程优化的相位调整技术
公开(公告)号：US20140053117A1
公开(公告)日：2014-02-20
申请号：US13997565
申请日：2011-12-30
申请人： Paul A. Nyhus , Shem O. Ogadhoh , Swaminathan Sivakumar , Seongtae Jeong
发明人： Paul A. Nyhus , Shem O. Ogadhoh , Swaminathan Sivakumar , Seongtae Jeong
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G03F1/36 , G03F1/70 , G06F17/5068
摘要： Techniques are provided for determining how thick or how deep to make the phased regions of a lithography mask. One example embodiment provides a method that includes: providing first mask layout design including a first test set, and providing a second mask layout design including a second test set, wherein the second test set is larger than the first test set; simulating critical dimensions through focus of structures of interest in the first test set for a range of phase depths/thicknesses, and selecting an initial preferred mask phase depth/thickness based on results of the simulating; and generating a fast thick-mask model (FTM) at the initial preferred phase depth/thickness, and correcting the second test set of the second mask layout design using the FTM, thereby providing an optimized mask layout design. A mask having the optimized mask layout design may be implemented to give the optimum patterning.
摘要翻译：提供了用于确定制造光刻掩模的相位区域的厚度或深度的技术。一个示例性实施例提供了一种方法，其包括：提供包括第一测试集的第一掩模布局设计，以及提供包括第二测试集的第二掩模布局设计，其中所述第二测试集大于所述第一测试集; 通过针对一系列相位深度/厚度的第一测试集合中关注的结构的焦点来模拟关键尺寸，并且基于模拟结果选择初始优选的掩模相位深度/厚度; 并且以最初的优选相位深度/厚度生成快速厚掩模模型（FTM），并且使用FTM校正第二掩模布局设计的第二测试集，由此提供优化的掩模布局设计。可以实施具有优化的掩模布局设计的掩模以给出最佳图案化。

7. 发明申请

US20150348839A1 DIRECTED SELF ASSEMBLY OF BLOCK COPOLYMERS TO FORM VIAS ALIGNED WITH INTERCONNECTS 审中-公开
标题翻译：方向自组装块状共聚物形成与互连对齐的VIAS
公开(公告)号：US20150348839A1
公开(公告)日：2015-12-03
申请号：US14822865
申请日：2015-08-10
申请人： Paul A. Nyhus , Swaminathan Sivakumar , Robert Bristol
发明人： Paul A. Nyhus , Swaminathan Sivakumar , Robert Bristol
IPC分类号： H01L21/768 , H01L21/311 , H01L23/522 , H01L21/033
CPC分类号： H01L21/76877 , H01L21/0337 , H01L21/31144 , H01L21/76811 , H01L21/76816 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A method of an aspect includes forming an interconnect line etch opening in a hardmask layer. The hardmask layer is over a dielectric layer that has an interconnect line disposed therein. The interconnect line etch opening is formed aligned over the interconnect line. A block copolymer is introduced into the interconnect line etch opening. The block copolymer is assembled to form a plurality of assembled structures that are spaced along a length of the interconnect line etch opening. An assembled structure is directly aligned over the interconnect line that is disposed within the dielectric layer.
摘要翻译：一方面的方法包括在硬掩模层中形成互连线蚀刻开口。硬掩模层位于其中布置有互连线的电介质层上。互连线蚀刻开口在互连线上形成对准。将嵌段共聚物引入到互连线蚀刻开口中。嵌段共聚物被组装以形成沿着互连线蚀刻开口的长度间隔开的多个组装结构。组装的结构在设置在电介质层内的互连线上直接对准。

8. 发明授权

US08959465B2 Techniques for phase tuning for process optimization 有权
标题翻译：用于过程优化的相位调整技术
公开(公告)号：US08959465B2
公开(公告)日：2015-02-17
申请号：US13997565
申请日：2011-12-30
申请人： Paul A. Nyhus , Shem O. Ogadhoh , Swaminathan Sivakumar , Seongtae Jeong
发明人： Paul A. Nyhus , Shem O. Ogadhoh , Swaminathan Sivakumar , Seongtae Jeong
IPC分类号： G06F17/50 , G03F1/36 , G03F1/70
CPC分类号： G06F17/5009 , G03F1/36 , G03F1/70 , G06F17/5068
摘要： Techniques are provided for determining how thick or how deep to make the phased regions of a lithography mask. One example embodiment provides a method that includes: providing a first mask layout design including a first test set, and providing a second mask layout design including a second test set, wherein the second test set is larger than the first test set; simulating critical dimensions through focus of structures of interest in the first test set for a range of phase depths/thicknesses, and selecting an initial preferred mask phase depth/thickness based on results of the simulating; and generating a fast thick-mask model (FTM) at the initial preferred phase depth/thickness, and correcting the second test set of the second mask layout design using the FTM, thereby providing an optimized mask layout design. A mask having the optimized mask layout design may be implemented to give the optimum patterning.
摘要翻译：提供了用于确定制造光刻掩模的相位区域的厚度或深度的技术。一个示例性实施例提供了一种方法，其包括：提供包括第一测试集的第一掩模布局设计，以及提供包括第二测试集的第二掩模布局设计，其中所述第二测试集大于所述第一测试集; 通过针对一系列相位深度/厚度的第一测试集合中关注的结构的焦点来模拟关键尺寸，并且基于模拟结果选择初始优选的掩模相位深度/厚度; 并且以最初的优选相位深度/厚度生成快速厚掩模模型（FTM），并且使用FTM校正第二掩模布局设计的第二测试集，由此提供优化的掩模布局设计。可以实施具有优化的掩模布局设计的掩模以给出最佳图案化。

9. 发明申请

US20100068633A1 SUB-RESOLUTION ASSIST FEATURES 失效
标题翻译：分解辅助功能
公开(公告)号：US20100068633A1
公开(公告)日：2010-03-18
申请号：US12623615
申请日：2009-11-23
申请人： CHARLES H. WALLACE , Swaminathan Sam Sivakumar , Paul A. Nyhus
发明人： CHARLES H. WALLACE , Swaminathan Sam Sivakumar , Paul A. Nyhus
IPC分类号： G03F1/00
CPC分类号： G03F1/36
摘要： Systems and techniques relating to the layout and use of sub-resolution assist features. In one implementation, a mask includes a first feature and a second feature separated from each other by a gap and a sub-resolution assist feature bridging the gap between the first feature and the second feature.
摘要翻译：与分辨率辅助功能的布局和使用相关的系统和技术。在一个实现中，掩模包括通过间隙彼此分离的第一特征和第二特征，以及桥接第一特征和第二特征之间的间隙的子分辨率辅助特征。

10. 发明授权

US09625815B2 Exposure activated chemically amplified directed self-assembly (DSA) for back end of line (BEOL) pattern cutting and plugging 有权
公开(公告)号：US09625815B2
公开(公告)日：2017-04-18
申请号：US14039140
申请日：2013-09-27
申请人： Paul A. Nyhus , Eungnak Han , Swaminathan Sivakumar , Ernisse S. Putna
发明人： Paul A. Nyhus , Eungnak Han , Swaminathan Sivakumar , Ernisse S. Putna
IPC分类号： H01L21/768 , H01L21/027 , G03F7/039 , H01L21/033 , H01L21/3105 , H01L21/32 , G03F7/00
CPC分类号： G03F7/0392 , B81C1/00428 , B81C2201/0149 , G03F7/0002 , G03F7/0045 , G03F7/038 , G03F7/039 , G03F7/11 , G03F7/16 , G03F7/2004 , G03F7/2037 , G03F7/26 , H01L21/0337 , H01L21/31058 , H01L21/32 , H01L21/3205 , H01L21/32139 , H01L21/76816
摘要： Self-aligned via and plug patterning for back end of line (BEOL) interconnects are described. In an example, a structure for directed self-assembly includes a substrate and a block co-polymer structure disposed above the substrate. The block co-polymer structure has a polystyrene (PS) component and a polymethyl methacrylate (PMMA) component. One of the PS component or the PMMA component is photosensitive.

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