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1. 发明授权

US07599361B2 Wire-speed packet management in a multi-pipeline network processor 有权
标题翻译：多线路网络处理器中的线速分组管理
公开(公告)号：US07599361B2
公开(公告)日：2009-10-06
申请号：US10882305
申请日：2004-07-02
申请人： Oren Malerevich
发明人： Oren Malerevich
IPC分类号： H04L12/28 , G06F13/00
CPC分类号： H04L49/3009 , H04L45/7453 , H04L2012/5685
摘要： A flow-identification content addressable memory (FICAM) comprising a row of content addressable memory (CAM) cells operable to store a first flow-identification. The first flow-identification corresponds to a first packet dispatched for processing by a pipeline unit (PU) belonging to a network processor. A comparison unit compares a second flow-identification corresponding to a second packet with contents of said at least a row of CAM cells. The comparison unit is further capable of determining if the second flow-identification is same as the first flow-identification. A flow identification eraser is provided for removing the first flow-identification from said at least a row of CAM cells upon determination by the comparison unit that the second flow-identification is same as the first flow-identification.
摘要翻译：流识别内容可寻址存储器（FICAM），其包括可操作以存储第一流标识的内容可寻址存储器（CAM）单元行。第一流标识对应于由属于网络处理器的流水线单元（PU）处理调度的第一分组。比较单元将对应于第二分组的第二流标识与所述至少一行CAM单元的内容进行比较。比较单元还能够确定第二流标识是否与第一流标识相同。提供流识别擦除器，用于在由比较单元确定第二流标识与第一流标识相同时，从所述至少一行CAM单元中去除第一流标识。

2. 发明授权

US06611538B1 Data transmission synchronization system 失效
标题翻译：数据传输同步系统
公开(公告)号：US06611538B1
公开(公告)日：2003-08-26
申请号：US09321469
申请日：1999-05-27
申请人： Oren Malerevich , Ilan Shimony
发明人： Oren Malerevich , Ilan Shimony
IPC分类号： H04J306
CPC分类号： H04L7/042 , H04L2007/045
摘要： An apparatus and method for providing synchronization in a data transmission system via the use of a short cyclic synchronization sequence inserted in the header of cells to be transmitted. A 2-bit sync sequence is inserted at the beginning of the header in each cell. At the receiving end, a pair of state machines search for and track the sync sequence. A feedback signal is generated that is used by the receiver to adjust its framing so as to align the received data with the boundaries of the cells. To aid in detecting the sync sequence, the two sync bits are rotated each cell cycle. To avoid confusion with data that mimics the sync sequence, the transmitter transmits idle cells containing all ones except for the 2-bit sync sequence field during the period that the receiver is attempting to sync up with the transmitter.
摘要翻译：一种用于在数据传输系统中提供同步的装置和方法，所述装置和方法通过使用插入要发送的小区头部的短循环同步序列。在每个单元格的头部的开头插入2位同步序列。在接收端，一对状态机搜索并跟踪同步序列。产生反馈信号，由接收机使用该反馈信号来调整其成帧，以使接收到的数据与单元格的边界对齐。为了帮助检测同步序列，每个单元周期旋转两个同步位。为了避免与模拟同步序列的数据混淆，在接收机试图与发射机同步的时间段期间，发射机发送包含除2位同步序列字段之外的所有信息的空闲信元。

3. 发明授权

US08385210B1 System and method for detection and delay control in a network environment 有权
标题翻译：用于网络环境中的检测和延迟控制的系统和方法
公开(公告)号：US08385210B1
公开(公告)日：2013-02-26
申请号：US12338892
申请日：2008-12-18
申请人： Ofer Weill , Ori Finkelman , Oren Malerevich , Kobi Vaknin , Yaniv Azran
发明人： Ofer Weill , Ori Finkelman , Oren Malerevich , Kobi Vaknin , Yaniv Azran
IPC分类号： H04L12/56
CPC分类号： H04L47/6215 , H04L47/56 , H04L47/623 , H04L47/6275
摘要： A method is provided in one example embodiment and includes indentifying a delay within one or more queues in a service element by evaluating a type of packet sought for processing in the service element. The method also includes comparing the delay to a threshold value to determine whether to adjust a processing mode of the service element. In more specific embodiments, the method includes providing a flow table that maps specific packets of a flow traversing the service element for receiving a certain amount of processing from a processor engine. The adjustment can include avoiding opening new flows for the service element, or providing continued service to a selected few flows and not others, or avoiding processing for certain types of services having less priority.
摘要翻译：在一个示例实施例中提供了一种方法，并且包括通过评估为服务元素中的处理而寻求的分组的类型来识别服务元素中的一个或多个队列内的延迟。该方法还包括将延迟与阈值进行比较，以确定是否调整服务元素的处理模式。在更具体的实施例中，该方法包括提供流表，其映射遍历服务元件的流的特定分组，用于从处理器引擎接收一定量的处理。该调整可以包括避免为服务元件打开新的流，或者为选定的几个流而不是其他流提供持续的服务，或避免对具有较低优先权的某些类型的服务的处理。

4. 发明申请

US20060002392A1 Wire-speed packet management in a multi-pipeline network processor 有权
公开(公告)号：US20060002392A1
公开(公告)日：2006-01-05
申请号：US10882305
申请日：2004-07-02
申请人： Oren Malerevich
发明人： Oren Malerevich
IPC分类号： H04L12/28
CPC分类号： H04L49/3009 , H04L45/7453 , H04L2012/5685
摘要： A flow-identification content addressable memory (FICAM) comprising a row of content addressable memory (CAM) cells operable to store a first flow-identification. The first flow-identification corresponds to a first packet dispatched for processing by a pipeline unit (PU) belonging to a network processor. A comparison unit compares a second flow-identification corresponding to a second packet with contents of said at least a row of CAM cells. The comparison unit is further capable of determining if the second flow-identification is same as the first flow-identification. A flow identification eraser is provided for removing the first flow-identification from said at least a row of CAM cells upon determination by the comparison unit that the second flow-identification is same as the first flow-identification.

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