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1. 发明授权

US06219807B1 Semiconductor memory device having an ECC circuit 有权
标题翻译：具有ECC电路的半导体存储器件
公开(公告)号：US06219807B1
公开(公告)日：2001-04-17
申请号：US09190620
申请日：1998-11-12
申请人： Nobuyuki Ebihara , Masami Ochiai
发明人： Nobuyuki Ebihara , Masami Ochiai
IPC分类号： G11C2900
CPC分类号： G06F11/1008 , G11C29/18
摘要： To provide a semiconductor memory device having an ECC circuit whereof checker-data inspection of memory cells in the user areas and the ECC areas can be performed at once, the ECC code generation circuit generates the ECC code of six bits whereof logic of each bit has XOR logic of each of six different combinations of 15 bits of the data set of 32 bits, and addresses in every user areas of the bit-columns are arranged in an order of 1, 4, 2, 5, 3, 6, . . . , b, f. When a checkerboard pattern is written, a first data set having 32 bits of logic ‘0’ and a second data set having 32 bits of logic ‘1’ are written alternately, in addresses 4n to 4n+3 and 4(n+1) to 4(n+1)+3 of the user areas on odd-numbered word-lines, and written alternately on even-numbered word-lines in an inverse order of the odd-numbered word-lines, when checker-data inspection of the memory-cell array is performed, n being an integer not less than 0.
摘要翻译：为了提供具有ECC电路的半导体存储器件，其可以一次执行用户区域和ECC区域中的存储器单元的检查数据检查，ECC代码生成电路生成六位的ECC码，每位的逻辑具有 32位数据组的15位的六个不同组合中的每一个的异或逻辑，以及位列的每个用户区域中的地址以1,2,4，2，5，3，6，...的顺序排列。。。，b，f。当写入棋盘图形时，在地址4n至4n + 3和4（n + 1）中交替地写入具有32位逻辑“0”的第一数据组和32位逻辑“1”的第二数据组，到奇数字线上的用户区域中的4（n + 1）+3个，并且以奇数字线的相反顺序交替地写入偶数字线上，当检查器数据检查执行存储单元阵列，n是不小于0的整数。

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