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1. 发明授权

US4648050A Color index conversion system in graphic display device 失效
标题翻译：图形显示装置中的颜色指标转换系统
公开(公告)号：US4648050A
公开(公告)日：1987-03-03
申请号：US629973
申请日：1984-07-11
申请人： Nobuhiko Yamagami
发明人： Nobuhiko Yamagami
IPC分类号： G09G5/06 , G09G5/02 , G09G1/00
CPC分类号： G09G5/022
摘要： A color graphic display device for converting color index data read out from a plurality of frame memories to color information on a screen so as to perform graphic display has a first register for holding a group number determined in accordance with a combination of areas between copy source and destination memories of the plurality of frame memories for an interarea copy, and a ROM table for storing conversion color index data at a plurality of addresses of the group number and for receiving as address data linked data of an output from the first register and the color index data from the plurality of frame memories. The group number is set in the first register and the corresponding color index data is read out from the frame memories, thereby obtaining updated or converted color index data from the ROM table. The color graphic display device also has a second register for holding write enable/disable data for specifying the write enable/disable mode of the plurality of frame memories. The write enable/disable data is set in the second register so as to specify the copy destination frame memories, and the specific bits of the converted color index data are thereby selectively written only in the copy destination frame memories.
摘要翻译：一种用于将从多个帧存储器读出的颜色索引数据转换为屏幕上的颜色信息以进行图形显示的彩色图形显示装置具有用于保存根据复制源之间的区域的组合确定的组号的第一寄存器以及用于区域间复制的多个帧存储器的目的地存储器，以及用于存储组号的多个地址处的转换颜色索引数据的ROM表，并且用于接收来自第一寄存器的输出的地址数据链接数据和来自多个帧存储器的颜色索引数据。组号被设置在第一寄存器中，并且从帧存储器读出相应的颜色索引数据，从而从ROM表获得更新或转换的颜色索引数据。彩色图形显示装置还具有用于保持用于指定多个帧存储器的写入使能/禁止模式的写入使能/禁止数据的第二寄存器。写入使能/禁止数据被设置在第二寄存器中以便指定复制目的地帧存储器，并且由此有选择地仅在复制目的地帧存储器中写入转换后的颜色索引数据的特定位。

2. 发明授权

US4823282A Graphic display apparatus having boundary detection target region designating circuit 失效
标题翻译：具有边界检测对象区域指定电路的图形显示装置
公开(公告)号：US4823282A
公开(公告)日：1989-04-18
申请号：US911060
申请日：1986-09-24
申请人： Nobuhiko Yamagami
发明人： Nobuhiko Yamagami
IPC分类号： G06F3/153 , G06T11/40 , G09G5/393 , G06F15/72
CPC分类号： G09G5/393 , G06T11/40
摘要： A boundary detection target region designating circuit includes a maximum value register in which a predetermined minimum value is initially set, and a minimum value register in which a predetermined maximum value is initially set. The content of the maximum value register is compared with a vertex coordinate of a boundary written in a boundary detection memory by a first comparator. If it is detected that the vertex coordinate is larger than the content of the maximum value register, the content of the maximum value register is updated to be the vertex coordinate by a first updating means. The content of the minimum value register is compared with the vertex coordinate by a second comparator. If it is detected that the vertex coordinate is smaller than the content of the minimum value register, the content of the minimum value register is updated to be the vertex coordinate by a second updating means. After a boundary write operation into the boundary detection memory is completed, maximum and minimum coordinates of a minimum rectangular region including all the boundaries of blanked-out regions are indicated by the maximum and minimum value registers.
摘要翻译：边界检测对象区域指定电路包括初始设定了规定的最小值的最大值寄存器和初始设定了规定的最大值的最小值寄存器。将最大值寄存器的内容与通过第一比较器写入边界检测存储器的边界的顶点坐标进行比较。如果检测到顶点坐标大于最大值寄存器的内容，则通过第一更新装置将最大值寄存器的内容更新为顶点坐标。通过第二比较器将最小值寄存器的内容与顶点坐标进行比较。如果检测到顶点坐标小于最小值寄存器的内容，则通过第二更新装置将最小值寄存器的内容更新为顶点坐标。在边界检测存储器的边界写入操作完成之后，由最大值和最小值寄存器指示包括所有消隐区域的所有边界的最小矩形区域的最大和最小坐标。

3. 发明授权

US4538144A Graphic display device having graphic generator for shading graphs 失效
标题翻译：具有用于阴影图形的图形生成器的图形显示装置
公开(公告)号：US4538144A
公开(公告)日：1985-08-27
申请号：US340387
申请日：1982-01-18
申请人： Nobuhiko Yamagami
发明人： Nobuhiko Yamagami
IPC分类号： G09G5/36 , G06K15/22 , G09G1/10 , G09G5/42 , G09G1/16
CPC分类号： G09G1/10 , G06K15/22 , G09G5/42
摘要： A graphic display device for shading the region between one straight line L.sub.1 connecting two points P.sub.1 and P.sub.2 and another straight line L.sub.2 parallel to the Y axis or the X axis, including a straight line coordinates generator to define a line L.sub.1 which connects the two points P.sub.1 and P.sub.2, an X or Y coordinates generator to count X or Y coordinates from a point T.sub.t on the line L.sub.1 given by the straight line coordinates generator in a predetermined direction, a controller for signalling the straight line coordinates generator when the X or Y coordinates generator completes generation of the coordinates for a selected shading line, a detector for detecting the intersections of the lines L.sub.1 and L.sub.2 in accordance with the number of the lattice points designated to provide shading on a selected shading line, a changer for changing the counting direction of the X or Y coordinates generator after detecting the intersection of the lines L.sub.1 and L.sub.2, and a shading display device to shade a region between the lines L.sub.1 and L.sub.2 in accordance with the coordinates of the lattice points designated to provide shading as designated by the straight line coordinates generator and the X or Y coordinates generator for the shading lines. The graphic display device sequentially generates shading lines parallel to either the X-axis or the Y-axis lightening the designated lattice points of a CRT or an X-Y plotter until all of the area between the two lines is shaded, thus simplifying the circuit architecture of the device.
摘要翻译：一种用于使连接两点P1和P2的一条直线L1与平行于Y轴或X轴的另一条直线L2之间的区域遮蔽的图形显示装置，包括直线坐标发生器，用于限定连接两点的线L1 P1和P2，X或Y坐标发生器，用于根据由直线坐标发生器沿预定方向给出的线L1上的点Tt计算X或Y坐标;控制器，用于当X或Y 坐标发生器完成对所选阴影线的坐标的生成，检测器，用于根据指定为在所选择的阴影线上提供阴影的点阵数来检测线L1和L2的交点;更换器，用于改变计数检测线L1和L2的交点之后的X或Y坐标发生器的方向，以及阴影显示装置，根据被指定为提供由直线坐标发生器指定的阴影的坐标和用于阴影线的X或Y坐标发生器的线L1和L2。图形显示装置顺序地生成平行于X轴或Y轴的阴影线，减轻CRT或XY绘图仪的指定格点，直到两行之间的所有区域都被遮蔽为止，从而简化了电路结构装置。

4. 发明授权

US4703230A Raster operation circuit 失效
标题翻译：光栅操作电路
公开(公告)号：US4703230A
公开(公告)日：1987-10-27
申请号：US900516
申请日：1986-08-26
申请人： Nobuhiko Yamagami
发明人： Nobuhiko Yamagami
IPC分类号： G09G5/20 , G09G5/393 , H01J29/70 , H01J29/72
CPC分类号： G09G5/393 , G09G5/20
摘要： In a graphic display apparatus having a digital differential analyzer (DDA), a chrominance data stored in a register is written in an area of a bit map memory defined by coordinates generated from DDA by a write control circuit in response to ARDY signal. A first flip-flop is reset by a busy signal from the write control circuit and is set by a load signal. When the first flip-flop is in a reset state, a first gate produces PRDY signal requesting a microprocessor to load the chrominance data in the register in response to RDY signal indicating completion of a coordinate setting operation from DDA. When the first flip-flop is in a set state, a second gate generates CRDY signal in response to RDY signal. CRDY and RDY signals are supplied to a selector which selects one of them due to a second flip-flop for switching a line processing mode and a raster operation mode, and supplies the selected signal to the write control circuit to thereby perform write operation.
摘要翻译：在具有数字差分分析器（DDA）的图形显示装置中，存储在寄存器中的色度数据被写入由位于由DDA产生的坐标的位图存储器的区域中，该位置由写入控制电路响应ARDY信号。第一触发器由来自写入控制电路的忙信号复位，并由负载信号设置。当第一触发器处于复位状态时，响应于指示从DDA完成坐标设置操作的RDY信号，第一门产生请求微处理器将色度数据加载到寄存器中的PRDY信号。当第一触发器处于置位状态时，第二栅极响应RDY信号产生CRDY信号。 CRDY和RDY信号被提供给选择器中的一个，由于用于切换线路处理模式和光栅操作模式的第二触发器，并且将所选择的信号提供给写入控制电路从而执行写入操作。

5. 发明授权

US4479192A Straight line coordinates generator 失效
标题翻译：直线坐标发生器
公开(公告)号：US4479192A
公开(公告)日：1984-10-23
申请号：US341579
申请日：1982-01-21
申请人： Nobuhiko Yamagami
发明人： Nobuhiko Yamagami
IPC分类号： G09G1/10 , G09G5/20 , G06F3/153
CPC分类号： G09G1/10 , G09G5/20
摘要： A new and improved straight line coordinates generator to determine and generate the coordinates of a group of lattice points [P.sub.k (k=1, 2, . . . , n-1)] to simulate an actual line defined by connecting the two lattice points P.sub.O (X.sub.o, Y.sub.o) and P.sub.n (X.sub.n, Y.sub.n), on a secondary coordinates face comprises registers, adders, comparators, a clock generator gate circuit, X-coordinate counter for determining X-coordinate values, Y-coordinate counter for determining Y-coordinate values, an initializing device for setting the registers with initial normalizing values and a generator for sequentially generating each X and Y coordinate of the lattice points to simulate the line. The circuit arrangement of the straight line coordinates generator is simplified by eliminating the need for decimal points in determining the coordinates of the lattice points to be lightened or highlighted to form the simulated line.
摘要翻译：一个新的和改进的直线坐标发生器来确定和生成一组格点[Pk（k = 1,2，...，n-1）]的坐标，以模拟通过连接两个格点定义的实际线次坐标面上的PO（Xo，Yo）和Pn（Xn，Yn）包括寄存器，加法器，比较器，时钟发生器门电路，用于确定X坐标值的X坐标计数器，用于确定Y的Y坐标计数器 - 初始化装置，用于设置具有初始归一化值的寄存器，以及用于顺序地生成格点的每个X和Y坐标以产生线的发生器。通过在确定要点亮或突出显示的格点的坐标以形成模拟线时不需要小数点来简化直线坐标发生器的电路布置。

6. 发明授权

US5031114A Method and apparatus for clipping figures against a clipping frame using line segment cross point and area detection 失效
标题翻译：用于使用线段交叉点和区域检测来剪裁针对帧的图像的方法和装置
公开(公告)号：US5031114A
公开(公告)日：1991-07-09
申请号：US175349
申请日：1988-03-30
申请人： Nobuhiko Yamagami
发明人： Nobuhiko Yamagami
IPC分类号： G06T11/00 , G06T15/30
CPC分类号： G06T15/30
摘要： In order to clip a figure using a predetermined frame, coordinate values of cross points defined by a line segment representing a figure to be clipped and each side of the clipping frame or each extension line thereof are detected. A positional relationship between the line segment and the clipping frame, and the presence/absence of the cross points on the clipping frame are obtained, respectively. By utilizing the above information, a new boundary line which does not exist in a figure before clipping can be extracted. Since the detection of cross point coordinates and the extraction of boundaries are independently processed, high-speed processing can be realized.
摘要翻译：为了使用预定的帧来剪辑图形，检测由表示待剪切的图形的线段和剪切帧的每一边或其每个延伸线的线段所定义的交叉点的坐标值。分别获得线段和剪辑帧之间的位置关系以及剪辑帧上的交叉点的存在/不存在。通过利用上述信息，可以提取在剪切之前不存在于图中的新的边界线。由于交叉点坐标的检测和边界的提取被独立处理，因此可以实现高速处理。

7. 发明授权

US5829032A Multiprocessor system 失效
标题翻译：多处理器系统
公开(公告)号：US5829032A
公开(公告)日：1998-10-27
申请号：US550403
申请日：1995-10-30
申请人： Hiroshi Komuro , Hiroo Hayashi , Nobuhiko Yamagami
发明人： Hiroshi Komuro , Hiroo Hayashi , Nobuhiko Yamagami
IPC分类号： G06F13/36 , G06F12/08
CPC分类号： G06F12/0813 , G06F2212/2542
摘要： As much tag information as corresponds to the number of blocks stored in main memories is stored in tag memories. The tag information indicates whether or not a processor belonging to a node other than the nodes containing tag memories has made an access request and the contents of a cache have been rewritten. Bus bridges perform cache coherency control, referring to the tag information. When the tag information indicates "Modified," the bus bridges stop the data read from the main memories and send the correct data to the requesting processor after a copy-back process of the modified block has been completed.
摘要翻译：与存储在主存储器中的块的数量相对应的标签信息被存储在标签存储器中。标签信息指示属于除包含标签存储器的节点之外的节点的处理器是否进行了访问请求，并且高速缓存的内容已被重写。总线桥执行缓存一致性控制，参考标签信息。当标签信息指示“修改”时，总线桥接器停止从主存储器读取的数据，并且在修改的块的复制过程完成之后将正确的数据发送到请求处理器。

8. 发明授权

US5754820A Microprocessor system with cache memory for eliminating unnecessary invalidation of cache data 失效
标题翻译：具有高速缓存存储器的微处理器系统，用于消除高速缓存数据的不必要的无效
公开(公告)号：US5754820A
公开(公告)日：1998-05-19
申请号：US440118
申请日：1995-05-12
申请人： Nobuhiko Yamagami
发明人： Nobuhiko Yamagami
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0888
摘要： In a cache memory control apparatus, a cache hit ratio of a cache memory is increased by employing both of control information (cacheable or non-cacheable) and condition information (invalidation or validation) to avoid unnecessary invalidation of the cache data. The microprocessor system with a cache memory control apparatus includes a microprocessor for processing various data. A main memory unit stores main data in a designated physical address allocated by a page unit. An auxiliary memory unit stores auxiliary data in a designated physical address allocated by a page unit. A cache memory temporarily stores a portion of the main data to be stored in the main memory unit. A virtual memory space manages by a virtual address to transfer the main data between the microprocessor and the main memory unit through the cache memory and also to transfer the auxiliary data between the microprocessor and the auxiliary memory units. A virtual memory control unit controls the virtual memory space and outputs an indicating information of cacheable or non-cacheable. A register stores a mode value which is given from the microprocessor to discriminate data from the microprocessor to be stored in the main memory unit or in the auxiliary memory units. A cache memory control unit lets the cache memory be cacheable or non-cacheable based upon the indicating information from the virtual memory control unit and, in a case of non-cacheable and the mode value discriminating the data from the microprocessor to be stored in the auxiliary memory units, lets the microprocessor directly access the auxiliary memory units and lets the cache memory keep valid.
摘要翻译：在高速缓冲存储器控制装置中，通过采用控制信息（可缓存或不可缓存）和条件信息（无效或验证）两者来增加高速缓存存储器的高速缓存命中率，以避免高速缓存数据的不必要的无效。具有高速缓冲存储器控制装置的微处理器系统包括用于处理各种数据的微处理器。主存储单元将主数据存储在由页单元分配的指定物理地址中。辅助存储单元将辅助数据存储在由页单元分配的指定物理地址中。缓存存储器临时存储要存储在主存储器单元中的主数据的一部分。虚拟存储器空间通过虚拟地址进行管理，以通过高速缓冲存储器在微处理器和主存储器单元之间传送主数据，并且还可以在微处理器和辅助存储器单元之间传送辅助数据。虚拟存储器控制单元控制虚拟存储器空间并输出可缓存或不可缓存的指示信息。寄存器存储从微处理器给出的模式值，以区分来自微处理器的数据以存储在主存储器单元或辅助存储器单元中。高速缓存存储器控制单元使得高速缓冲存储器可以基于来自虚拟存储器控制单元的指示信息而被缓存或不可缓存，并且在不可高速缓存的情况下，并且模式值将来自微处理器的数据识别为存储在辅助存储器单元，让微处理器直接访问辅助存储器单元，并使缓存存储器保持有效。

9. 发明授权

US4583163A Data prefetch apparatus 失效
标题翻译：数据预取装置
公开(公告)号：US4583163A
公开(公告)日：1986-04-15
申请号：US408739
申请日：1982-08-17
申请人： Yoshiyuki Kobayashi , Nobuhiko Yamagami , Jyun-ichi Kihara
发明人： Yoshiyuki Kobayashi , Nobuhiko Yamagami , Jyun-ichi Kihara
IPC分类号： G06F3/06 , G06F5/06 , G06F5/14 , G06F9/38 , G06F13/12 , G06F13/28
CPC分类号： G06F9/383 , G06F13/122 , G06F13/28
摘要： A data prefetch apparatus provided between a main memory formed of a plurality of memory blocks and an I/O device whose data transfer speed is slower than that of the main memory, comprising an address counter for the main memory and a data buffer for storing the data prefetched from the main memory. In the data prefetch apparatus, a full/empty detector is connected to the data buffer and a memory block detector is connected to the address counter and the data prefetch is interrupted when the over-access of the one of the memory block is detected and is restarted when the data buffer is empty and data request is supplied from the I/O device.
摘要翻译：一种数据预取装置，设置在由多个存储块形成的主存储器和数据传输速度低于主存储器的I / O装置之间，包括用于主存储器的地址计数器和用于存储从主存储器预取的数据。在数据预取装置中，将完整/空检测器连接到数据缓冲器，并且存储器块检测器连接到地址计数器，并且当检测到存储块中的一个的过度访问时，数据预取被中断，并且是当数据缓冲区为空并且从I / O设备提供数据请求时重新启动。

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