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1. 发明授权

US08612312B1 Electronically managing items in a wish list 有权
标题翻译：电子管理愿望清单中的项目
公开(公告)号：US08612312B1
公开(公告)日：2013-12-17
申请号：US13076317
申请日：2011-03-30
申请人： Matthew M. Edwards , Nitin Bansal , Jacob D. Cohen , Jeffrey J. Hsu , Don Le
发明人： Matthew M. Edwards , Nitin Bansal , Jacob D. Cohen , Jeffrey J. Hsu , Don Le
IPC分类号： G06Q30/00
CPC分类号： G06Q30/0633
摘要： Systems and methods are provided for electronically managing items in a wish list. In some embodiments, order information associated with an order of one or more items may be received. The order may be associated with a purchasing customer, and may indicate that the purchasing customer is purchasing the one or more items of the order. One or more wish lists that were presented to the purchasing customer prior to receiving the order may be determined. For each of the one or more wish lists that were presented to the purchasing customer, it may be determined whether at least one of the items of the order is referenced in the wish list. The reference to the ordered item may then be removed from at least one of the wish lists.
摘要翻译：提供了用于电子管理愿望清单中的项目的系统和方法。在一些实施例中，可以接收与一个或多个项目的订单相关联的订单信息。该订单可能与采购客户相关联，并且可以指示采购客户正在购买订单的一个或多个项目。可以确定在接收订单之前呈现给采购客户的一个或多个愿望清单。对于呈现给购买客户的一个或多个愿望清单中的每一个，可以确定在该愿望清单中是否引用了该订单中的至少一个项目。然后可以从至少一个希望列表中移除对订购商品的引用。

2. 发明申请

US20110167629A1 AREA-EFFICIENT DISTRIBUTED DEVICE STRUCTURE FOR INTEGRATED VOLTAGE REGULATORS 有权
标题翻译：集成电压调节器的区域分布式器件结构
公开(公告)号：US20110167629A1
公开(公告)日：2011-07-14
申请号：US13071110
申请日：2011-03-24
申请人： Joshipura JWALANT , Nitin BANSAL , Amit KATYAL , Massimiliano PICCA
发明人： Joshipura JWALANT , Nitin BANSAL , Amit KATYAL , Massimiliano PICCA
IPC分类号： H01R43/00
CPC分类号： H05K3/30 , G06F17/5063 , Y10T29/49002 , Y10T29/4913 , Y10T29/49169
摘要： An area efficient distributed device for integrated voltage regulators comprising at least one filler cell connected between a pair of PADS on I/O rail of a chip and at least one additional filler cell having small size replica of said device is coupled to said I/O rails for distributing replicas of said device on the periphery of said chip. The device is connected as small size replica on the lower portion of said second filler cell for distributing said device on the periphery of said chip and providing maximal area utilization.
摘要翻译：一种用于集成电压调节器的区域有效的分布式装置，其包括连接在芯片的I / O轨上的一对PADS与至少一个具有所述装置的小尺寸复制品的附加填充单元之间的填充单元耦合到所述I / O 用于在所述芯片的外围分配所述设备的副本的轨道。该装置作为小尺寸复制品连接在所述第二填充单元的下部，用于在所述芯片的周围分配所述装置并提供最大的面积利用率。

3. 发明授权

US08754620B2 Voltage regulator 有权
标题翻译：电压调节器
公开(公告)号：US08754620B2
公开(公告)日：2014-06-17
申请号：US12698328
申请日：2010-02-02
申请人： Nitin Bansal , Kallol Chatterjee
发明人： Nitin Bansal , Kallol Chatterjee
IPC分类号： G05F1/00
CPC分类号： G05F1/575
摘要： Described herein are principles for designing and operating a voltage regulator that will function stably and accurately without an external capacitance for all or a wide range of load circuits and characteristics of load circuits. In accordance with some of these principles, a voltage regulator is disclosed having multiple feedback loops, each responding to transients with different speeds, that operate in parallel to adjust an output current of the regulator in response to variations in the output current/voltage due to, for example, variations in a supply voltage and/or variations in a load current. In this way, a voltage regulator can respond quickly to variations in the output current/voltage and can avoid entering an unstable state.
摘要翻译：这里描述的是用于设计和操作电压调节器的原理，其将稳定且准确地运行，而无需外部电容用于所有或宽范围的负载电路和负载电路的特性。根据这些原理中的一些，公开了一种电压调节器，其具有多个反馈回路，每个响应于不同速度的瞬变，其并联操作以响应于由于输出电流/电压的变化而调节调节器的输出电流，例如，电源电压的变化和/或负载电流的变化。以这种方式，电压调节器可以快速响应输出电流/电压的变化，并且可以避免进入不稳定状态。

4. 发明授权

US08710809B2 Voltage regulator structure that is operationally stable for both low and high capacitive loads 有权
标题翻译：对于低电容负载和高容性负载都可操作稳定的稳压器结构
公开(公告)号：US08710809B2
公开(公告)日：2014-04-29
申请号：US13170679
申请日：2011-06-28
申请人： Rupesh Khare , Nitin Bansal
发明人： Rupesh Khare , Nitin Bansal
IPC分类号： G05F1/00
CPC分类号： G05F1/563
摘要： A regulator structure includes a first differential amplifier having a first input coupled to a reference voltage node. A second differential amplifier has a first input coupled to the output of the first differential amplifier. A third differential amplifier has a first input coupled to the output of the first differential amplifier. A first pmos transistor has its gate coupled to the second differential amplifier output, and its drain coupled to a second input of each of the first and second differential amplifiers. A second pmos transistor has its gate coupled to the third differential amplifier output, and its drain configured to output a regulated voltage which is also a second input of the third differential amplifier. A circuit is configured to replicate the regulated voltage and couple the replicated regulated voltage to the drain of the first pmos transistor.
摘要翻译：调节器结构包括具有耦合到参考电压节点的第一输入的第一差分放大器。第二差分放大器具有耦合到第一差分放大器的输出的第一输入。第三差分放大器具有耦合到第一差分放大器的输出的第一输入。第一pmos晶体管的栅极耦合到第二差分放大器输出，其漏极耦合到第一和第二差分放大器中的每一个的第二输入端。第二pmos晶体管的栅极耦合到第三差分放大器输出，其漏极被配置为输出也是第三差分放大器的第二输入的调节电压。电路被配置为复制经调节的电压并将复制的调节电压耦合到第一pmos晶体管的漏极。

5. 发明申请

US20100164469A1 On-chip power management 有权
标题翻译：片上电源管理
公开(公告)号：US20100164469A1
公开(公告)日：2010-07-01
申请号：US12592942
申请日：2009-12-04
申请人： Nitin Bansal
发明人： Nitin Bansal
IPC分类号： H02J1/00
CPC分类号： H02J1/00 , G06F1/26 , H02M1/36
摘要： The present disclosure teaches a power management device for providing one or more voltages and prohibiting the operation until the IC is initialized and voltage stability is achieved. The power management device includes a power regulator block and a masking block. The power regulator block includes one or more of the following elements: -a regulator, a bandgap reference generator, a low voltage detector LVDD, a low voltage detector LVDM, and a plurality of logic gates. In one embodiment, the masking block includes one or more level shifters, a plurality of logic gates, a D flip-flop, and a power on reset circuit (PoR).
摘要翻译：本公开教导了用于提供一个或多个电压并且禁止操作的电力管理装置，直到IC被初始化并且实现了电压稳定性。电源管理装置包括电源调节器块和屏蔽块。功率调节器块包括以下元件中的一个或多个：调节器，带隙基准发生器，低电压检测器LVDD，低电压检测器LVDM和多个逻辑门。在一个实施例中，屏蔽块包括一个或多个电平移位器，多个逻辑门，D触发器和上电复位电路（PoR）。

6. 发明授权

US06952091B2 Integrated low dropout linear voltage regulator with improved current limiting 有权
标题翻译：集成低压差线性稳压器，具有改进的电流限制
公开(公告)号：US06952091B2
公开(公告)日：2005-10-04
申请号：US10731884
申请日：2003-12-09
申请人： Nitin Bansal
发明人： Nitin Bansal
IPC分类号： G05F1/575 , G05F1/573
CPC分类号： G05F1/575
摘要： An integrated Low Dropout (LDO) linear voltage regulator provides improved current limiting. A differential voltage amplifier compares an output voltage to reference voltage and controls a pass transistor to make the output voltage substantially match the reference voltage. This is accomplished by sensing the output voltage of the voltage regulator for application to a first input of the differential amplifier and coupling a second input of the differential amplifier to the reference voltage. A current sense transistor utilizes current mirroring techniques to sense the current passing through the pass transistor to the output. This sensed current is compared to a reference current. The result of that comparison is fed back to the differential voltage amplifier to in a manner that increases the apparently sensed output voltage in situations where the sensed current exceeds the reference current.
摘要翻译：集成的低压差（LDO）线性稳压器提供改进的电流限制。差分电压放大器将输出电压与参考电压进行比较，并且控制通过晶体管以使输出电压基本上与参考电压相匹配。这是通过感测电压调节器的输出电压来实现的，以将其应用于差分放大器的第一输入并将差分放大器的第二输入端耦合到参考电压。电流检测晶体管利用电流镜像技术来检测通过传输晶体管的电流到输出。将该感测电流与参考电流进行比较。该比较的结果被反馈到差分电压放大器，以在感测电流超过参考电流的情况下增加明显感测的输出电压。

7. 发明授权

US08909948B2 On-chip power management 有权
标题翻译：片上电源管理
公开(公告)号：US08909948B2
公开(公告)日：2014-12-09
申请号：US12592942
申请日：2009-12-04
申请人： Nitin Bansal
发明人： Nitin Bansal
IPC分类号： H02J1/00 , G06F1/26 , H02M1/36
CPC分类号： H02J1/00 , G06F1/26 , H02M1/36
摘要： The present disclosure teaches a power management device for providing one or more voltages and prohibiting the operation until the IC is initialized and voltage stability is achieved. The power management device includes a power regulator block and a masking block. The power regulator block includes one or more of the following elements:- a regulator, a bandgap reference generator, a low voltage detector LVDD, a low voltage detector LVDM, and a plurality of logic gates. In one embodiment, the masking block includes one or more level shifters, a plurality of logic gates, a D flip-flop, and a power on reset circuit (PoR).
摘要翻译：本公开教导了用于提供一个或多个电压并且禁止操作的电力管理装置，直到IC被初始化并且实现了电压稳定性。电源管理装置包括电源调节器块和屏蔽块。功率调节器块包括以下元件中的一个或多个：调节器，带隙基准发生器，低电压检测器LVDD，低电压检测器LVDM和多个逻辑门。在一个实施例中，屏蔽块包括一个或多个电平移位器，多个逻辑门，D触发器和上电复位电路（PoR）。

8. 发明授权

US08426924B2 Area-efficient distributed device structure for integrated voltage regulators 有权
标题翻译：集成稳压器的区域效率分布式器件结构
公开(公告)号：US08426924B2
公开(公告)日：2013-04-23
申请号：US13071110
申请日：2011-03-24
申请人： Joshipura Jwalant , Nitin Bansal , Amit Katyal , Massimiliano Picca
发明人： Joshipura Jwalant , Nitin Bansal , Amit Katyal , Massimiliano Picca
IPC分类号： H01L27/11 , H01L27/118
CPC分类号： H05K3/30 , G06F17/5063 , Y10T29/49002 , Y10T29/4913 , Y10T29/49169
摘要： An area efficient distributed device for integrated voltage regulators comprising at least one filler cell coupled between a pair of PADS on I/O rail of a chip and at least one additional filler cell having small size replica of said device is coupled to said I/O rails for distributing replicas of said device on the periphery of said chip. The device is coupled as small size replica on the lower portion of said second filler cell for distributing said device on the periphery of said chip and providing maximal area utilization.
摘要翻译：一种用于集成电压调节器的区域有效的分布式装置，其包括耦合在芯片的I / O轨上的一对PADS与至少一个具有所述装置的小尺寸复制品的附加填充单元之间的填充单元耦合到所述I / O 用于在所述芯片的外围分配所述设备的副本的轨道。该装置作为小尺寸复制件耦合在所述第二填充单元的下部，用于将所述装置分配在所述芯片的外围并提供最大的面积利用率。

9. 发明授权

US08045353B2 Integrated circuit capable of operating at different supply voltages 有权
标题翻译：能够在不同电源电压下工作的集成电路
公开(公告)号：US08045353B2
公开(公告)日：2011-10-25
申请号：US11645815
申请日：2006-12-26
申请人： Nitin Bansal
发明人： Nitin Bansal
IPC分类号： H02M1/00
CPC分类号： H01L23/5286 , H01L24/06 , H01L27/0207 , H01L2924/13091 , H01L2924/14 , H01L2924/00
摘要： A chip configuration for dual board voltage compatibility comprising ballast I/O pads, regulator control block and VDDCO pad. If 1.8V is available on board, all 1.8V pads are connected to the package pins and the VDDCO pad is double bonded with one 1.8V package pin. This ensures that the regulator is in operation providing 1.2V supply to the core. If 1.2V is available on board, all 1.2V pads are bonded to the package pins and VDDCO pad is left unbonded. A weak pulldown ensures that the regulator is inoperational and the gate voltage of ballast transistor is pulled up. Now 1.2V pads directly get supply from the board through package pins and is provided to the core without suffering IR drop.
摘要翻译：双板电压兼容性的芯片配置，包括镇流器I / O焊盘，调节器控制块和VDDCO焊盘。如果板载1.8V，所有1.8V焊盘都连接到封装引脚，并且VDDCO焊盘与1.8V封装引脚双重连接。这确保了稳压器在运行时向核心提供1.2V电源。如果板载1.2V，则所有1.2V焊盘均焊接到封装引脚上，并且VDDCO焊盘未连接。弱下拉确保调节器不工作，并且镇流器晶体管的栅极电压被拉高。现在，1.2V焊盘直接通过封装引脚从板上供电，并提供给核心，而不会受到红外线损坏。

10. 发明授权

US07664704B2 Clearing receivables with improved search 有权
标题翻译：清算应收款，改进搜索
公开(公告)号：US07664704B2
公开(公告)日：2010-02-16
申请号：US11322570
申请日：2005-12-30
申请人： Volker Ripp , Nitin Bansal , Dietmar Nowotny
发明人： Volker Ripp , Nitin Bansal , Dietmar Nowotny
IPC分类号： G06Q40/00
CPC分类号： G06Q30/04 , G06Q20/102 , G06Q20/1085
摘要： A system and method match payments with invoices. A payment is received from a business partner. Multiple fields of an invoice database are concatenated to form a single string per record, and a search for an invoice corresponding to the payment is performed. The search may be a fuzzy search based on a search string created from information associated with the payment.
摘要翻译：系统和方法将付款与发票相匹配。从业务伙伴收到付款。发票数据库的多个字段连接以形成每个记录的单个字符串，并且执行与付款相对应的发票的搜索。搜索可以是基于从与支付相关联的信息创建的搜索字符串的模糊搜索。

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