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1. 发明授权

US5038120A Frequency modulated phase locked loop with fractional divider and jitter compensation 失效
$Frequency modulated phase locked loop with fractional divider and jitter compensation$
标题翻译：频率调制锁相环，具有分数分频和抖动补偿
公开(公告)号：US5038120A
公开(公告)日：1991-08-06
申请号：US486781
申请日：1990-03-01
申请人： Mark A. Wheatley , Leslie A. Lepper , Nigel K. Webb
发明人： Mark A. Wheatley , Leslie A. Lepper , Nigel K. Webb
IPC分类号： H03C3/02 , H03C3/09 , H03L7/197
CPC分类号： H03C3/0991 , H03C3/0925 , H03C3/0933 , H03C3/0941 , H03C3/0958 , H03C3/0975 , H03L7/1976 , H03C3/02
摘要： A fractional-N type frequency synthesizer has a voltage controlled oscillator controlled in a phase-locked loop by a divide by N divider and a phase comparator responsive to the divided frequency and to a reference frequency Fr. An accumulator is responsive to the desired fractional part of the N and is clocked by Fr to produce carry signals for producing the required periodic variations in N. A second accumulator produces periodic equal and opposite further variations in N to reduce the magnitude of the error waveform which would be given to the phase-detector output by the variations in n caused by the first accumulator. A digital to analog converter and a differentiating circuit produce a jitter correction signal for reducing residual jitter. A coherent detector detects for the presence of any residual jitter at the control input of the VCO and resulting from the fractional-N control circuit. Any such residual jitter produces a control signal which adjusts the value of the jitter correction signal accordingly. Two-port frequency modulation is produced by an in-band circuit incorporating an integrator and a full band circuit. With no FM input, a counter detects any divergence in output frequency from the desired value and caused by spurious input at the integrator. A resultant control signal offsets any such spurious inputs. The coherent detector detects at the control input of the VCO any component which is coherent with the in band modulation signal and adjusts the full band modulation signal to eliminate this, so that correct FM is produced.
摘要翻译：分数N型频率合成器具有通过除以N除法器和相位比较器在锁相环中控制的压控振荡器，该相位比较器响应于分频和参考频率Fr。累加器响应于期望的N分数部分并由Fr计时，以产生用于产生N中所需的周期性变化的进位信号。第二个累加器在N中产生周期性相等和相反的其他变化，以减小误差波形的幅度这将由由第一累加器引起的n的变化给予相位检测器输出。数模转换器和微分电路产生抖动校正信号，以减少残余抖动。相干检测器检测在VCO的控制输入处是否存在任何残留抖动，并由分数N控制电路产生。任何这样的残余抖动产生相应地调整抖动校正信号的值的控制信号。双端口频率调制由并入有积分器和全频带电路的带内电路产生。在没有FM输入的情况下，计数器会从所需值检测输出频率的任何偏差，并由积分器的寄生输入引起。所得到的控制信号抵消任何这样的虚假输入。相干检测器在VCO的控制输入处检测与带内调制信号相干的任何分量，并调整全频带调制信号以消除该频带调制信号，从而产生正确的FM。

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